]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
arm64: dts: rockchip: assign pipe clock to rk356x PCIe lanes
authorDavid Heidelberg <david@ixit.cz>
Wed, 4 Mar 2026 11:05:27 +0000 (12:05 +0100)
committerHeiko Stuebner <heiko@sntech.de>
Tue, 24 Mar 2026 22:23:22 +0000 (23:23 +0100)
These clocks are used by PCIe lanes, but we're missing from the
definition.

Suggested-by: Charalampos Mitrodimas <charmitro@posteo.net>
Signed-off-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://patch.msgid.link/20260304-rk3568-bri-r2-pro-fix-pcie-v4-1-37abd7ba29d0@ixit.cz
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm64/boot/dts/rockchip/rk3568.dtsi
arch/arm64/boot/dts/rockchip/rk356x-base.dtsi

index 658097ed69714a82f6e7e8870bc35fc285ad1b86..3bc653f027f1fe35c68b2fb332833efbef159700 100644 (file)
                bus-range = <0x10 0x1f>;
                clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
                         <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
-                        <&cru CLK_PCIE30X1_AUX_NDFT>;
+                        <&cru CLK_PCIE30X1_AUX_NDFT>,
+                        <&cru CLK_PCIE30X1_PIPE_DFT>;
                clock-names = "aclk_mst", "aclk_slv",
-                             "aclk_dbi", "pclk", "aux";
+                             "aclk_dbi", "pclk", "aux",
+                             "pipe";
                device_type = "pci";
                interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
                bus-range = <0x20 0x2f>;
                clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
                         <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
-                        <&cru CLK_PCIE30X2_AUX_NDFT>;
+                        <&cru CLK_PCIE30X2_AUX_NDFT>,
+                        <&cru CLK_PCIE30X2_PIPE_DFT>;
                clock-names = "aclk_mst", "aclk_slv",
-                             "aclk_dbi", "pclk", "aux";
+                             "aclk_dbi", "pclk", "aux",
+                             "pipe";
                device_type = "pci";
                interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
index c8321af7de7dd97e5faa2cc3603988b84bfdd99a..64bdd8b7754b5a0673280e44261d75b27bcf29a1 100644 (file)
                bus-range = <0x0 0xf>;
                clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
                         <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
-                        <&cru CLK_PCIE20_AUX_NDFT>;
+                        <&cru CLK_PCIE20_AUX_NDFT>,
+                        <&cru CLK_PCIE20_PIPE_DFT>;
                clock-names = "aclk_mst", "aclk_slv",
-                             "aclk_dbi", "pclk", "aux";
+                             "aclk_dbi", "pclk", "aux",
+                             "pipe";
                device_type = "pci";
                #interrupt-cells = <1>;
                interrupt-map-mask = <0 0 0 7>;