Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index da873cc4ee838be69f823d1fd23b578c2200c79e..6d2584bff8542ed90d91de05c72f9f07787cd09a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,40 @@
+2020-11-17  Sebastian Pop  <spop@amazon.com>
+
+       Backported from master:
+       2020-11-17  Sebastian Pop  <spop@amazon.com>
+
+       * config.gcc: add configure flags --with-{cpu,arch,tune}-{32,64}
+       as alias flags for --with-{cpu,arch,tune} on AArch64.
+       * doc/install.texi: Document new flags for aarch64.
+
+2020-11-17  Sebastian Pop  <spop@amazon.com>
+
+       Backported from master:
+       2020-11-17  Sebastian Pop  <spop@amazon.com>
+
+       * config.gcc: Add --with-tune to AArch64 configure flags.
+
+2020-11-17  Tamar Christina  <tamar.christina@arm.com>
+
+       PR target/97535
+       * config/aarch64/aarch64.c (aarch64_expand_cpymem): Use unsigned
+       arithmetic in check.
+
+2020-11-17  Monk Chiang  <monk.chiang@sifive.com>
+
+       Backported from master:
+       2020-11-14  Monk Chiang  <monk.chiang@sifive.com>
+
+       PR target/97682
+       * config/riscv/riscv.h (RISCV_PROLOGUE_TEMP_REGNUM): Change register
+       to t0.
+       (RISCV_CALL_ADDRESS_TEMP_REGNUM): New Marco, define t1 register.
+       (RISCV_CALL_ADDRESS_TEMP): Use it for call instructions.
+       * config/riscv/riscv.c (riscv_legitimize_call_address): Use
+       RISCV_CALL_ADDRESS_TEMP.
+       (riscv_compute_frame_info): Change temporary register to t0 form t1.
+       (riscv_trampoline_init): Adjust comment.
+
 2020-11-16  Cui,Lili  <lili.cui@intel.com>
 
        * config/i386/i386.h: Add PREFETCHW to march=broadwell.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 0ad54ab67bd8a1dd3dfe3aba692afb1b1e90841b..6ee7c2ae987a5cbf2a7bcad4930b8b70d5682306 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201117
+20201118

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b559c794d08c95aabe95424415751ac4d4d27903..1a71f8cbc6f66b026314459507fac9b4fa1ea342 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,26 @@
+2020-11-17  Tamar Christina  <tamar.christina@arm.com>
+
+       Backported from master:
+       2020-10-28  Tamar Christina  <tamar.christina@arm.com>
+
+       PR target/97535
+       * gcc.target/aarch64/pr97535.c: Exclude ILP32.
+
+2020-11-17  Tamar Christina  <tamar.christina@arm.com>
+
+       PR target/97535
+       * gcc.target/aarch64/pr97535.c: New test.
+
+2020-11-17  Monk Chiang  <monk.chiang@sifive.com>
+
+       Backported from master:
+       2020-11-14  Monk Chiang  <monk.chiang@sifive.com>
+
+       PR target/97682
+       * g++.target/riscv/pr97682.C: New test.
+       * gcc.target/riscv/interrupt-3.c: Check register for t0.
+       * gcc.target/riscv/interrupt-4.c: Likewise.
+
 2020-11-13  Thomas Schwinge  <thomas@codesourcery.com>
 
        Backported from master:

diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index ccc011196867ad4bb9426217435add0e79e3f359..f64e1d6676a26ea1a8562e86da5ad3eaa814bd45 100644 (file)
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,15 @@
+2020-11-17  Patrick Palka  <ppalka@redhat.com>
+
+       Backported from master:
+       2020-11-17  Patrick Palka  <ppalka@redhat.com>
+
+       PR libstdc++/97828
+       * include/bits/ranges_algo.h (__search_n_fn::operator()): Check
+       random_access_iterator before using the backtracking
+       implementation.  When the backwards scan fails prematurely,
+       reset __remainder appropriately.
+       * testsuite/25_algorithms/search_n/97828.cc: New test.
+
 2020-11-16  Jonathan Wakely  <jwakely@redhat.com>
 
        Backported from master: