arm64: dts: mediatek: mt8195: Correct clock order for dp_intf*

[ Upstream commit 51bc68debab9e30b50c6352315950f3cfc309b32 ]

The clocks for dp_intf* device nodes are given in the wrong order,
causing the binding validation to fail.

Fixes: 6c2503b5856a ("arm64: dts: mt8195: Add dp-intf nodes")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20240802070951.1086616-1-wenst@chromium.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 2ee45752583c00330c90cb92db742324c2b0a4fe..98c15eb68589a5a453486f7eaf6d074b1e6ab1f6 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -3251,10 +3251,10 @@
                        compatible = "mediatek,mt8195-dp-intf";
                        reg = <0 0x1c015000 0 0x1000>;
                        interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
-                       clocks = <&vdosys0  CLK_VDO0_DP_INTF0>,
-                                <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
+                       clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
+                                <&vdosys0  CLK_VDO0_DP_INTF0>,
                                 <&apmixedsys CLK_APMIXED_TVDPLL1>;
-                       clock-names = "engine", "pixel", "pll";
+                       clock-names = "pixel", "engine", "pll";
                        status = "disabled";
                };
 
@@ -3521,10 +3521,10 @@
                        reg = <0 0x1c113000 0 0x1000>;
                        interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
                        power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
-                       clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
-                                <&vdosys1 CLK_VDO1_DPINTF>,
+                       clocks = <&vdosys1 CLK_VDO1_DPINTF>,
+                                <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
                                 <&apmixedsys CLK_APMIXED_TVDPLL2>;
-                       clock-names = "engine", "pixel", "pll";
+                       clock-names = "pixel", "engine", "pll";
                        status = "disabled";
                };