arm64: dts: qcom: qcs8300: add the pcie smmu node

Add the PCIe SMMU node to enable address translations
for pcie.

Reviewed-by: Dmitry Baryshkov <lumag@kernel.org>
Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250508-qcs8300-pcie-smmu-v3-1-c6b4453b0b22@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 9bc6cf9a3495a026cc5b51c2c3ba9f07cbcf5744..009f9658a4fa8b14e1a81a47622298d1aadafcdb 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -5127,6 +5127,81 @@
                                     <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>;
                };
 
+               pcie_smmu: iommu@15200000 {
+                       compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+                       reg = <0x0 0x15200000 0x0 0x80000>;
+                       #iommu-cells = <2>;
+                       #global-interrupts = <2>;
+                       dma-coherent;
+
+                       interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
                intc: interrupt-controller@17a00000 {
                        compatible = "arm,gic-v3";
                        reg = <0x0 0x17a00000 0x0 0x10000>,