[riscv] Add missing volatile qualifiers on timer and seed CSR accesses

The timer and entropy seed CSRs will, by design, return different
values each time they are read.

Add the missing volatile qualifiers on the inline assembly to prevent
gcc from assuming that repeated invocations may be elided.

Signed-off-by: Michael Brown <mcb30@ipxe.org>

diff --git a/src/arch/riscv/core/zicntr.c b/src/arch/riscv/core/zicntr.c
index 0ba453c75cec3ff25a0136fa0be71207ac4ca8a4..826f31a68d57ca0c8d8e13af5e41241a9dc85ca1 100644 (file)
--- a/src/arch/riscv/core/zicntr.c
+++ b/src/arch/riscv/core/zicntr.c
@@ -64,7 +64,7 @@ rdtime_low ( void ) {
        unsigned long time;
 
        /* Read low XLEN bits of current time */
-       __asm__ ( "rdtime %0" : "=r" ( time ) );
+       __asm__ __volatile__ ( "rdtime %0" : "=r" ( time ) );
        return time;
 }
 
@@ -86,14 +86,15 @@ rdtime_scaled ( void ) {
 
        /* Read full current time */
 #if __riscv_xlen >= 64
-       __asm__ ( "rdtime %0" : "=r" ( u.time ) );
+       __asm__ __volatile__ ( "rdtime %0" : "=r" ( u.time ) );
 #else
-       __asm__ ( "1:\n\t"
-                 "rdtimeh %1\n\t"
-                 "rdtime %0\n\t"
-                 "rdtimeh %2\n\t"
-                 "bne %1, %2, 1b\n\t"
-                 : "=r" ( u.low ), "=r" ( u.high ), "=r" ( tmp ) );
+       __asm__ __volatile__ ( "1:\n\t"
+                              "rdtimeh %1\n\t"
+                              "rdtime %0\n\t"
+                              "rdtimeh %2\n\t"
+                              "bne %1, %2, 1b\n\t"
+                              : "=r" ( u.low ), "=r" ( u.high ),
+                                "=r" ( tmp ) );
 #endif
 
        /* Scale time to avoid XLEN-bit rollover */

diff --git a/src/arch/riscv/core/zkr.c b/src/arch/riscv/core/zkr.c
index 5cb44c2d0fdd6ff5656176b5a2e9f313d2daebaa..bf16096711428535992abfff78d63b3c0f13412a 100644 (file)
--- a/src/arch/riscv/core/zkr.c
+++ b/src/arch/riscv/core/zkr.c
@@ -85,7 +85,8 @@ static int zkr_get_noise ( noise_sample_t *noise ) {
        for ( i = 0 ; i < ZKR_SEED_MAX_RETRY ; i++ ) {
 
                /* Read seed CSR */
-               __asm__ ( "csrrw %0, seed, zero" : "=r" ( seed ) );
+               __asm__ __volatile__ ( "csrrw %0, seed, zero" :
+                                      "=r" ( seed ) );
 
                /* Check operationsl state */
                if ( ( seed & ZKR_SEED_OPST_MASK ) == ZKR_SEED_OPST_ES16 ) {