media: ccs-pll: Start VT pre-PLL multiplier search from correct value

The ccs_pll_calculate_vt_tree() function does a search over possible VT
PLL configurations to find the "best" one. If the sensor does not support
odd pre-PLL divisors and the minimum value (with constraints) isn't 1,
other odd values could be errorneously searched (and selected) for the
pre-PLL divisor. Fix this.

Fixes: 415ddd993978 ("media: ccs-pll: Split limits and PLL configuration into front and back parts")
Cc: stable@vger.kernel.org
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>

diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index e516ed23e899d35651e750fe7ca2169e2a18e63d..2399cd6509b757601e9ac007aa9e1033066c69e5 100644 (file)
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -397,6 +397,8 @@ static int ccs_pll_calculate_vt_tree(struct device *dev,
        min_pre_pll_clk_div = max_t(u16, min_pre_pll_clk_div,
                                    pll->ext_clk_freq_hz /
                                    lim_fr->max_pll_ip_clk_freq_hz);
+       if (!(pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER))
+               min_pre_pll_clk_div = clk_div_even(min_pre_pll_clk_div);
 
        dev_dbg(dev, "vt min/max_pre_pll_clk_div: %u,%u\n",
                min_pre_pll_clk_div, max_pre_pll_clk_div);