assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
timeout-sec = <40>;
+ bootph-all;
};
cgc1: clock-controller@292c0000 {
clocks = <&clk IMX93_CLK_WDOG3_GATE>;
timeout-sec = <40>;
status = "disabled";
+ bootph-all;
};
wdog4: watchdog@424a0000 {
clocks = <&clk IMX93_CLK_WDOG4_GATE>;
timeout-sec = <40>;
status = "disabled";
+ bootph-all;
};
wdog5: watchdog@424b0000 {
clocks = <&clk IMX93_CLK_WDOG5_GATE>;
timeout-sec = <40>;
status = "disabled";
+ bootph-all;
};
tpm3: pwm@424e0000 {
timeout-sec = <40>;
fsl,ext-reset-output;
status = "disabled";
+ bootph-all;
+ };
+
+ wdog4: watchdog@49230000 {
+ compatible = "fsl,imx94-wdt", "fsl,imx93-wdt";
+ reg = <0x49230000 0x10000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>;
+ timeout-sec = <40>;
+ fsl,ext-reset-output;
+ status = "disabled";
+ bootph-all;
};
};
clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
timeout-sec = <40>;
status = "disabled";
+ bootph-all;
+ };
+
+ wdog4: watchdog@424a0000 {
+ compatible = "fsl,imx93-wdt";
+ reg = <0x424a0000 0x10000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ timeout-sec = <40>;
+ status = "disabled";
+ bootph-all;
};
tpm3: pwm@424e0000 {
clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>;
timeout-sec = <40>;
status = "disabled";
+ bootph-all;
+ };
+
+ wdog4: watchdog@420c0000 {
+ compatible = "fsl,imx93-wdt";
+ reg = <0x420c0000 0x10000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ timeout-sec = <40>;
+ status = "disabled";
+ bootph-all;
};
tpm3: pwm@42100000 {