ASoC: fsl_sai: Add missing registers to cache default

[ Upstream commit 90ed688792a6b7012b3e8a2f858bc3fe7454d0eb ]

Drivers does cache sync during runtime resume, setting all writable
registers. Not all writable registers are set in cache default, resulting
in the erorr message:
  fsl-sai 30c30000.sai: using zero-initialized flat cache, this may cause
  unexpected behavior

Fix this by adding missing writable register defaults.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Link: https://patch.msgid.link/20251216102246.676181-1-alexander.stein@ew.tq-group.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 0de878d64a3bd184ab45d86a9526f98c16b7707f..95a502ec3a05773fdbc81c6a64fc2e07471b5ce7 100644 (file)
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -979,6 +979,7 @@ static struct reg_default fsl_sai_reg_defaults_ofs0[] = {
        {FSL_SAI_TDR6, 0},
        {FSL_SAI_TDR7, 0},
        {FSL_SAI_TMR, 0},
+       {FSL_SAI_TTCTL, 0},
        {FSL_SAI_RCR1(0), 0},
        {FSL_SAI_RCR2(0), 0},
        {FSL_SAI_RCR3(0), 0},
@@ -1002,12 +1003,14 @@ static struct reg_default fsl_sai_reg_defaults_ofs8[] = {
        {FSL_SAI_TDR6, 0},
        {FSL_SAI_TDR7, 0},
        {FSL_SAI_TMR, 0},
+       {FSL_SAI_TTCTL, 0},
        {FSL_SAI_RCR1(8), 0},
        {FSL_SAI_RCR2(8), 0},
        {FSL_SAI_RCR3(8), 0},
        {FSL_SAI_RCR4(8), 0},
        {FSL_SAI_RCR5(8), 0},
        {FSL_SAI_RMR, 0},
+       {FSL_SAI_RTCTL, 0},
        {FSL_SAI_MCTL, 0},
        {FSL_SAI_MDIV, 0},
 };