EDAC/synopsys: Use the correct register to disable the error interrupt on v3 hw

commit be76ceaf03bc04e74be5e28f608316b73c2b04ad upstream.

v3.x Synopsys EDAC DDR doesn't have the QOS Interrupt register. Use the
ECC Clear Register to disable the error interrupts instead.

Fixes: f7824ded4149 ("EDAC/synopsys: Add support for version 3 of the Synopsys EDAC DDR")
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Shubhrajyoti Datta <Shubhrajyoti.datta@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20220427015137.8406-2-sherry.sun@nxp.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index 40b1abeca8562e2b55dde35aa488e86beb2e9ee4..88a481043d4c3c0f63c348d22b2143522a9b7b04 100644 (file)
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -865,8 +865,11 @@ static void enable_intr(struct synps_edac_priv *priv)
 static void disable_intr(struct synps_edac_priv *priv)
 {
        /* Disable UE/CE Interrupts */
-       writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
-                       priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
+       if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
+               writel(0x0, priv->baseaddr + ECC_CLR_OFST);
+       else
+               writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
+                      priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
 }
 
 static int setup_irq(struct mem_ctl_info *mci,