staging: media: tegra-video: tegra20: increase maximum VI clock frequency

Increase maximum VI clock frequency to 450MHz to allow correct work with
high resolution camera sensors.

Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # tegra20, parallel camera
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>

diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/media/tegra-video/tegra20.c
index 7ceefd920cd653d40ae6b8133589cb71b6dfe4ac..bf8755698610897bdca527b19ec45c667163ee7b 100644 (file)
--- a/drivers/staging/media/tegra-video/tegra20.c
+++ b/drivers/staging/media/tegra-video/tegra20.c
@@ -598,7 +598,7 @@ const struct tegra_vi_soc tegra20_vi_soc = {
        .ops = &tegra20_vi_ops,
        .hw_revision = 1,
        .vi_max_channels = 2, /* TEGRA_VI_OUT_1 and TEGRA_VI_OUT_2 */
-       .vi_max_clk_hz = 150000000,
+       .vi_max_clk_hz = 450000000,
        .has_h_v_flip = true,
 };