Fix PR80082: LDRD erronously used for 64bit load on ARMv7-R

2017-04-11  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    Backport from GCC 6
    2017-04-06  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    PR target/80082
    * config/arm/arm-protos.h (FL_LPAE): Define macro.
    (FL_FOR_ARCH7VE): Add FL_LPAE.
    (arm_arch_lpae): Declare extern.
    * config/arm/arm.c (arm_arch_lpae): Declare.
    (arm_option_override): Define arm_arch_lpae.
    * config/arm/arm.h (TARGET_HAVE_LPAE): Redefine in term of
    arm_arch_lpae.

    gcc/testsuite/
    PR target/80082
    * gcc.target/arm/atomic_loaddi_10.c: New testcase.
    * gcc.target/arm/atomic_loaddi_11.c: Likewise.

From-SVN: r246844

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 69ca2f75366c09dda3e42281c667c559d8e27466..4e1da819e9a0f45c5505b718e05d7fb08fc8b977 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2017-04-11  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+       Backport from GCC 6
+       2017-04-06  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+       PR target/80082
+       * config/arm/arm-protos.h (FL_LPAE): Define macro.
+       (FL_FOR_ARCH7VE): Add FL_LPAE.
+       (arm_arch_lpae): Declare extern.
+       * config/arm/arm.c (arm_arch_lpae): Declare.
+       (arm_option_override): Define arm_arch_lpae.
+       * config/arm/arm.h (TARGET_HAVE_LPAE): Redefine in term of
+       arm_arch_lpae.
+
 2017-04-11  Martin Jambor  <mjambor@suse.cz>
 
        Backport from mainline

diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index ebaf746227723f68c4c1cda89ba35c598a3ae4ba..21df391789d3d9f7b1d28e2bb2f99458843d0c3e 100644 (file)
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -343,7 +343,7 @@ extern bool arm_is_constant_pool_ref (rtx);
 #define FL_STRONG     (1 << 8)       /* StrongARM */
 #define FL_ARCH5E     (1 << 9)        /* DSP extensions to v5 */
 #define FL_XSCALE     (1 << 10)              /* XScale */
-/* spare             (1 << 11) */
+#define FL_LPAE       (1 << 11)       /* ARMv7-A LPAE.  */
 #define FL_ARCH6      (1 << 12)       /* Architecture rel 6.  Adds
                                         media instructions.  */
 #define FL_VFPV2      (1 << 13)       /* Vector Floating Point V2.  */
@@ -392,7 +392,7 @@ extern bool arm_is_constant_pool_ref (rtx);
 #define FL_FOR_ARCH6M  (FL_FOR_ARCH6 & ~FL_NOTM)
 #define FL_FOR_ARCH7   ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
 #define FL_FOR_ARCH7A  (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
-#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV)
+#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV | FL_LPAE)
 #define FL_FOR_ARCH7R  (FL_FOR_ARCH7A | FL_THUMB_DIV)
 #define FL_FOR_ARCH7M  (FL_FOR_ARCH7 | FL_THUMB_DIV)
 #define FL_FOR_ARCH7EM  (FL_FOR_ARCH7M | FL_ARCH7EM)
@@ -487,6 +487,9 @@ extern int arm_arch_thumb2;
 extern int arm_arch_arm_hwdiv;
 extern int arm_arch_thumb_hwdiv;
 
+/* Nonzero if this chip supports the Large Physical Address Extension.  */
+extern int arm_arch_lpae;
+
 /* Nonzero if chip disallows volatile memory access in IT block.  */
 extern int arm_arch_no_volatile_ce;
 

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 6f9518995a387c84cd53deaa5ae6bac465d81ee8..c8aab8e09f83efd084a9d21e0d2fd04c04120877 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -866,6 +866,9 @@ int arm_arch_thumb2;
 int arm_arch_arm_hwdiv;
 int arm_arch_thumb_hwdiv;
 
+/* Nonzero if this chip supports the Large Physical Address Extension.  */
+int arm_arch_lpae;
+
 /* Nonzero if chip disallows volatile memory access in IT block.  */
 int arm_arch_no_volatile_ce;
 
@@ -2862,6 +2865,7 @@ arm_option_override (void)
   arm_arch_iwmmxt2 = (insn_flags & FL_IWMMXT2) != 0;
   arm_arch_thumb_hwdiv = (insn_flags & FL_THUMB_DIV) != 0;
   arm_arch_arm_hwdiv = (insn_flags & FL_ARM_DIV) != 0;
+  arm_arch_lpae = (insn_flags & FL_LPAE) != 0;
   arm_arch_no_volatile_ce = (insn_flags & FL_NO_VOLATILE_CE) != 0;
   arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
   arm_arch_crc = (insn_flags & FL_CRC32) != 0;

diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 5561e433b2929df311aec3263033c14b366836d3..4baf3e454b293c765c98948d86b23024ef84982d 100644 (file)
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -370,8 +370,7 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
 #define TARGET_HAVE_LDREX      ((arm_arch6 && TARGET_ARM) || arm_arch7)
 
 /* Nonzero if this chip supports LPAE.  */
-#define TARGET_HAVE_LPAE                                               \
-  (arm_arch7 && ((insn_flags & FL_FOR_ARCH7VE) == FL_FOR_ARCH7VE))
+#define TARGET_HAVE_LPAE       (arm_arch_lpae)
 
 /* Nonzero if this chip supports ldrex{bh} and strex{bh}.  */
 #define TARGET_HAVE_LDREXBH    ((arm_arch6k && TARGET_ARM) || arm_arch7)

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 6b737b69feb734f204677be9d02b31d9aa8a68c2..d65d1ab7c368598b9d5d0cf2c10cf2e680f3f7e2 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2017-04-11  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+       Backport from GCC 6
+       2017-04-06  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+       PR target/80082
+       * gcc.target/arm/atomic_loaddi_10.c: New testcase.
+       * gcc.target/arm/atomic_loaddi_11.c: Likewise.
+
 2017-04-11  Martin Jambor  <mjambor@suse.cz>
 
        Backport from mainline

diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_10.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_10.c
new file mode 100644 (file)
index 0000000..ecc3d06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_10.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v7ve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v7ve } */
+
+#include <stdatomic.h>
+
+atomic_llong x = 0;
+
+atomic_llong get_x()
+{
+  return atomic_load(&x);
+}
+
+/* { dg-final { scan-assembler "ldrd" } } */

diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
new file mode 100644 (file)
index 0000000..85c64ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v7r_ok } */
+/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" "-march=*" } { "-mcpu=cortex-r5" } } */
+/* { dg-options "-O2 -mcpu=cortex-r5" } */
+
+#include <stdatomic.h>
+
+atomic_llong x = 0;
+
+atomic_llong get_x()
+{
+  return atomic_load(&x);
+}
+
+/* { dg-final { scan-assembler-not "ldrd" } } */