RISC-V: Add minimal support of double trap extension 1.0

Add support of double trap extension [1], enabling GCC
to recognize the following extensions at compile time.

New extensions:
    - ssdbltrp
    - smdbltrp

[1] https://github.com/riscv/riscv-double-trap/releases/download/v1.0/riscv-double-trap.pdf

gcc/ChangeLog:

	* config/riscv/riscv-ext.def: New extensions
	* config/riscv/riscv-ext.opt: Auto re-generated
	* doc/riscv-ext.texi: Auto re-generated

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/arch-57.c: New test
	* gcc.target/riscv/arch-58.c: New test

Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 97b576617adde80ac2e9f07abea3e37409aa6012..dbda8ded39747369b4d4b55310fb13be2f0837d7 100644 (file)
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1727,6 +1727,19 @@ DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ smdbltrp,
+  /* UPPERCAE_NAME */ SMDBLTRP,
+  /* FULL_NAME */ "Double Trap Extensions",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"zicsr"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ sm,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ ssaia,
   /* UPPERCAE_NAME */ SSAIA,
@@ -1818,6 +1831,19 @@ DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ ssdbltrp,
+  /* UPPERCAE_NAME */ SSDBLTRP,
+  /* FULL_NAME */ "Double Trap Extensions",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"zicsr"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ ss,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ supm,
   /* UPPERCAE_NAME */ SUPM,

diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index 9199aa31b42041045ddca64836a44ee7b1f2f4eb..5e9c5f56ad672f59c962c5bc6e9ded5b5ffd413f 100644 (file)
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -343,6 +343,8 @@ Mask(SMNPM) Var(riscv_sm_subext)
 
 Mask(SMSTATEEN) Var(riscv_sm_subext)
 
+Mask(SMDBLTRP) Var(riscv_sm_subext)
+
 Mask(SSAIA) Var(riscv_ss_subext)
 
 Mask(SSCOFPMF) Var(riscv_ss_subext)
@@ -357,6 +359,8 @@ Mask(SSTC) Var(riscv_ss_subext)
 
 Mask(SSSTRICT) Var(riscv_ss_subext)
 
+Mask(SSDBLTRP) Var(riscv_ss_subext)
+
 Mask(SUPM) Var(riscv_su_subext)
 
 Mask(SVINVAL) Var(riscv_sv_subext)

diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index bd3d29c75ab55d2b9a8a015f94c60835374e4d08..7a22d841d1b6277d594249d7b1870a971ec6c467 100644 (file)
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -510,6 +510,10 @@
 @tab 1.0
 @tab State enable extension
 
+@item smdbltrp
+@tab 1.0
+@tab Double Trap Extensions
+
 @item ssaia
 @tab 1.0
 @tab Advanced interrupt architecture extension for supervisor-mode
@@ -538,6 +542,10 @@
 @tab 1.0
 @tab ssstrict extension
 
+@item ssdbltrp
+@tab 1.0
+@tab Double Trap Extensions
+
 @item supm
 @tab 1.0
 @tab supm extension

diff --git a/gcc/testsuite/gcc.target/riscv/arch-57.c b/gcc/testsuite/gcc.target/riscv/arch-57.c
new file mode 100644 (file)
index 0000000..08d3761
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-57.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_smdbltrp -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_zicsr2p0_smdbltrp1p0\"" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/arch-58.c b/gcc/testsuite/gcc.target/riscv/arch-58.c
new file mode 100644 (file)
index 0000000..1481da5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-58.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_ssdbltrp -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_zicsr2p0_ssdbltrp1p0\"" } } */