ARM: dts: renesas: r8a7742: Move interrupt-parent to root node

Move the "interrupt-parent = <&gic>" property from the soc node to the
root node, and simplify "interrupts-extended = <&gic ...>" to
"interrupts = <...>".

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://patch.msgid.link/eab2e4860569e877e66b2f35940ba00e5ec7ff55.1759414774.git.geert+renesas@glider.be

diff --git a/arch/arm/boot/dts/renesas/r8a7742.dtsi b/arch/arm/boot/dts/renesas/r8a7742.dtsi
index 9083d288cc339dd7b0767d2122707325adbb1024..4220b2349b4091f952bf36baca957070ce5ef991 100644 (file)
--- a/arch/arm/boot/dts/renesas/r8a7742.dtsi
+++ b/arch/arm/boot/dts/renesas/r8a7742.dtsi
@@ -14,6 +14,7 @@
        compatible = "renesas,r8a7742";
        #address-cells = <2>;
        #size-cells = <2>;
+       interrupt-parent = <&gic>;
 
        /*
         * The external audio clocks are configured as 0 Hz fixed frequency
@@ -208,19 +209,19 @@
 
        pmu-0 {
                compatible = "arm,cortex-a15-pmu";
-               interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
-                                     <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
-                                     <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
-                                     <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
        };
 
        pmu-1 {
                compatible = "arm,cortex-a7-pmu";
-               interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
-                                     <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
-                                     <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
-                                     <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
        };
 
@@ -234,7 +235,6 @@
 
        soc {
                compatible = "simple-bus";
-               interrupt-parent = <&gic>;
 
                #address-cells = <2>;
                #size-cells = <2>;
@@ -1932,10 +1932,10 @@
 
        timer {
                compatible = "arm,armv7-timer";
-               interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
                interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
        };