[PATCH v2] RISC-V: Add svbare extension.

This patch support svbare extension, which is an extension in RVA23 profile.
To enable GCC to recognize and process svbare extension correctly at compile time.

gcc/ChangeLog:

	* config/riscv/riscv-ext.def: New extension defs.
	* config/riscv/riscv-ext.opt: Ditto.
	* doc/riscv-ext.texi: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/arch-60.c: New test.

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 2d052c15206829c47b0a0ffecfd1b255324692ff..c3d0bd42b200842dbec3d45c6e6b06b87ad3a4a1 100644 (file)
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1961,6 +1961,19 @@ DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ svbare,
+  /* UPPERCAE_NAME */ SVBARE,
+  /* FULL_NAME */ "Satp mode bare is supported",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"zicsr"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ sv,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 #include "riscv-ext-corev.def"
 #include "riscv-ext-sifive.def"
 #include "riscv-ext-thead.def"

diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index e0314430ffb11dbf557140676b4e191fd6f7214d..3e5cbb34898e421e53c62bde10ae2a56e7322135 100644 (file)
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -379,6 +379,8 @@ Mask(SVADU) Var(riscv_sv_subext)
 
 Mask(SVADE) Var(riscv_sv_subext)
 
+Mask(SVBARE) Var(riscv_sv_subext)
+
 Mask(XCVALU) Var(riscv_xcv_subext)
 
 Mask(XCVBI) Var(riscv_xcv_subext)

diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index e7e1f75cca6dba80f76ca299c0b77fd0ae0ae962..3e6541ac732b11fc2dc8dbe5318ae04b15742b81 100644 (file)
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -582,6 +582,10 @@
 @tab 1.0
 @tab Cause exception when hardware updating of A/D bits is disabled
 
+@item svbare
+@tab 1.0
+@tab Satp mode bare is supported
+
 @item xcvalu
 @tab 1.0
 @tab Core-V miscellaneous ALU extension

diff --git a/gcc/testsuite/gcc.target/riscv/arch-60.c b/gcc/testsuite/gcc.target/riscv/arch-60.c
new file mode 100644 (file)
index 0000000..ea599f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-60.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_svbare -mabi=lp64" } */
+int foo()
+{
+}