phy: qcom: qmp-pcie: Add support for Glymur PCIe Gen4x2 PHY

Glymur platform has two Gen4 2-lanes controllers, the fourth and
sixth instances. Add support for their PHYs.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20251224-phy-qcom-pcie-add-glymur-v3-2-57396145bc22@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 7671aed5635f4f7295136e734452caf41a37c5fa..fed2fc9bb31108d51f88d34f3379c7744681f485 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -4632,6 +4632,22 @@ static const struct qmp_phy_cfg glymur_qmp_gen5x4_pciephy_cfg = {
        .phy_status             = PHYSTATUS_4_20,
 };
 
+static const struct qmp_phy_cfg glymur_qmp_gen4x2_pciephy_cfg = {
+       .lanes = 2,
+
+       .offsets                = &qmp_pcie_offsets_v8_0,
+
+       .reset_list             = sdm845_pciephy_reset_l,
+       .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
+       .vreg_list              = qmp_phy_vreg_l,
+       .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
+
+       .regs                   = pciephy_v8_regs_layout,
+
+       .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
+       .phy_status             = PHYSTATUS_4_20,
+};
+
 static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
 {
        const struct qmp_phy_cfg *cfg = qmp->cfg;
@@ -5383,6 +5399,9 @@ err_node_put:
 
 static const struct of_device_id qmp_pcie_of_match_table[] = {
        {
+               .compatible = "qcom,glymur-qmp-gen4x2-pcie-phy",
+               .data = &glymur_qmp_gen4x2_pciephy_cfg,
+       }, {
                .compatible = "qcom,glymur-qmp-gen5x4-pcie-phy",
                .data = &glymur_qmp_gen5x4_pciephy_cfg,
        }, {