wifi: ath12k: add hardware registers for QCC2072

Add hardware registers and populate hw_regs field in
ath12k_wifi7_hw_ver_map for QCC2072. Note for some registers not
defined and not used by QCC2072, a magic value is assigned.

Also populate other fields to be the same with WCN7850. Among them,
however, QCC2072 requires different HAL ops and descriptor size, both
will be updated in upcoming patches.

Tested-on: QCC2072 hw1.0 PCI WLAN.COL.1.0-01560-QCACOLSWPL_V1_TO_SILICONZ-1
Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3

Signed-off-by: Baochen Qiang <baochen.qiang@oss.qualcomm.com>
Reviewed-by: Vasanthakumar Thiagarajan <vasanthakumar.thiagarajan@oss.qualcomm.com>
Link: https://patch.msgid.link/20260112-ath12k-support-qcc2072-v2-7-fc8ce1e43969@oss.qualcomm.com
Signed-off-by: Jeff Johnson <jeff.johnson@oss.qualcomm.com>

diff --git a/drivers/net/wireless/ath/ath12k/core.h b/drivers/net/wireless/ath/ath12k/core.h
index 31d5d10beb85ad17d41232ab5c4a1c6af6a2f275..667cf5993cf155a08bc26899453db1045b2e934d 100644 (file)
--- a/drivers/net/wireless/ath/ath12k/core.h
+++ b/drivers/net/wireless/ath/ath12k/core.h
@@ -155,6 +155,7 @@ enum ath12k_hw_rev {
        ATH12K_HW_QCN9274_HW20,
        ATH12K_HW_WCN7850_HW20,
        ATH12K_HW_IPQ5332_HW10,
+       ATH12K_HW_QCC2072_HW10,
 };
 
 enum ath12k_firmware_mode {

diff --git a/drivers/net/wireless/ath/ath12k/hal.h b/drivers/net/wireless/ath/ath12k/hal.h
index 81b0cb002b38cead90025095f110f4090c94c84b..94ecc035fc493125fc51d4ff53ba5a0fe782ab0a 100644 (file)
--- a/drivers/net/wireless/ath/ath12k/hal.h
+++ b/drivers/net/wireless/ath/ath12k/hal.h
@@ -1121,6 +1121,8 @@ struct ath12k_hw_hal_params {
        u32 wbm2sw_cc_enable;
 };
 
+#define ATH12K_HW_REG_UNDEFINED        0xdeadbeaf
+
 struct ath12k_hw_regs {
        u32 tcl1_ring_id;
        u32 tcl1_ring_misc;

diff --git a/drivers/net/wireless/ath/ath12k/wifi7/Makefile b/drivers/net/wireless/ath/ath12k/wifi7/Makefile
index dcfa732bb95bcb52b8fe3453aa84758deb6b0f47..45b561cdba4b13ac027f31360a0e19f336b12764 100644 (file)
--- a/drivers/net/wireless/ath/ath12k/wifi7/Makefile
+++ b/drivers/net/wireless/ath/ath12k/wifi7/Makefile
@@ -14,6 +14,7 @@ ath12k_wifi7-y += core.o \
                  dp_mon.o \
                  hal.o \
                  hal_qcn9274.o \
-                 hal_wcn7850.o
+                 hal_wcn7850.o \
+                 hal_qcc2072.o
 
 ath12k_wifi7-$(CONFIG_ATH12K_AHB) += ahb.o

diff --git a/drivers/net/wireless/ath/ath12k/wifi7/hal.c b/drivers/net/wireless/ath/ath12k/wifi7/hal.c
index 03a007dd6857fe0138d76239ef40991edb014809..b957ebc9b7c5c61b8245432089eb0e9d92d8ad3d 100644 (file)
--- a/drivers/net/wireless/ath/ath12k/wifi7/hal.c
+++ b/drivers/net/wireless/ath/ath12k/wifi7/hal.c
@@ -12,6 +12,7 @@
 #include "../hif.h"
 #include "hal_qcn9274.h"
 #include "hal_wcn7850.h"
+#include "hal_qcc2072.h"
 
 static const struct ath12k_hw_version_map ath12k_wifi7_hw_ver_map[] = {
        [ATH12K_HW_QCN9274_HW10] = {
@@ -42,6 +43,13 @@ static const struct ath12k_hw_version_map ath12k_wifi7_hw_ver_map[] = {
                .hal_params = &ath12k_hw_hal_params_ipq5332,
                .hw_regs = &ipq5332_regs,
        },
+       [ATH12K_HW_QCC2072_HW10] = {
+               .hal_ops = &hal_wcn7850_ops,
+               .hal_desc_sz = sizeof(struct hal_rx_desc_wcn7850),
+               .tcl_to_wbm_rbm_map = ath12k_hal_tcl_to_wbm_rbm_map_wcn7850,
+               .hal_params = &ath12k_hw_hal_params_wcn7850,
+               .hw_regs = &qcc2072_regs,
+       },
 };
 
 int ath12k_wifi7_hal_init(struct ath12k_base *ab)

diff --git a/drivers/net/wireless/ath/ath12k/wifi7/hal_qcc2072.c b/drivers/net/wireless/ath/ath12k/wifi7/hal_qcc2072.c
new file mode 100644 (file)
index 0000000..6c49860
--- /dev/null
+++ b/drivers/net/wireless/ath/ath12k/wifi7/hal_qcc2072.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: BSD-3-Clause-Clear
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include "hal_qcc2072.h"
+
+const struct ath12k_hw_regs qcc2072_regs = {
+       /* SW2TCL(x) R0 ring configuration address */
+       .tcl1_ring_id = 0x00000920,
+       .tcl1_ring_misc = 0x00000928,
+       .tcl1_ring_tp_addr_lsb = 0x00000934,
+       .tcl1_ring_tp_addr_msb = 0x00000938,
+       .tcl1_ring_consumer_int_setup_ix0 = 0x00000948,
+       .tcl1_ring_consumer_int_setup_ix1 = 0x0000094c,
+       .tcl1_ring_msi1_base_lsb = 0x00000960,
+       .tcl1_ring_msi1_base_msb = 0x00000964,
+       .tcl1_ring_msi1_data = 0x00000968,
+       .tcl_ring_base_lsb = 0x00000b70,
+       .tcl1_ring_base_lsb = 0x00000918,
+       .tcl1_ring_base_msb = 0x0000091c,
+       .tcl2_ring_base_lsb = 0x00000990,
+
+       /* TCL STATUS ring address */
+       .tcl_status_ring_base_lsb = 0x00000d50,
+
+       .wbm_idle_ring_base_lsb = 0x00000d3c,
+       .wbm_idle_ring_misc_addr = 0x00000d4c,
+       .wbm_r0_idle_list_cntl_addr = 0x00000240,
+       .wbm_r0_idle_list_size_addr = 0x00000244,
+       .wbm_scattered_ring_base_lsb = 0x00000250,
+       .wbm_scattered_ring_base_msb = 0x00000254,
+       .wbm_scattered_desc_head_info_ix0 = 0x00000260,
+       .wbm_scattered_desc_head_info_ix1 = 0x00000264,
+       .wbm_scattered_desc_tail_info_ix0 = 0x00000270,
+       .wbm_scattered_desc_tail_info_ix1 = 0x00000274,
+       .wbm_scattered_desc_ptr_hp_addr = 0x00000027c,
+
+       .wbm_sw_release_ring_base_lsb = 0x0000037c,
+       .wbm_sw1_release_ring_base_lsb = ATH12K_HW_REG_UNDEFINED,
+       .wbm0_release_ring_base_lsb = 0x00000e08,
+       .wbm1_release_ring_base_lsb = 0x00000e80,
+
+       /* PCIe base address */
+       .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,
+       .pcie_pcs_osc_dtct_config_base = 0x01e0cc58,
+
+       /* PPE release ring address */
+       .ppe_rel_ring_base = 0x0000046c,
+
+       /* REO DEST ring address */
+       .reo2_ring_base = 0x00000578,
+       .reo1_misc_ctrl_addr = 0x00000ba0,
+       .reo1_sw_cookie_cfg0 = 0x0000006c,
+       .reo1_sw_cookie_cfg1 = 0x00000070,
+       .reo1_qdesc_lut_base0 = ATH12K_HW_REG_UNDEFINED,
+       .reo1_qdesc_lut_base1 = ATH12K_HW_REG_UNDEFINED,
+
+       .reo1_ring_base_lsb = 0x00000500,
+       .reo1_ring_base_msb = 0x00000504,
+       .reo1_ring_id = 0x00000508,
+       .reo1_ring_misc = 0x00000510,
+       .reo1_ring_hp_addr_lsb = 0x00000514,
+       .reo1_ring_hp_addr_msb = 0x00000518,
+       .reo1_ring_producer_int_setup = 0x00000524,
+       .reo1_ring_msi1_base_lsb = 0x00000548,
+       .reo1_ring_msi1_base_msb = 0x0000054c,
+       .reo1_ring_msi1_data = 0x00000550,
+       .reo1_aging_thres_ix0 = 0x00000b2c,
+       .reo1_aging_thres_ix1 = 0x00000b30,
+       .reo1_aging_thres_ix2 = 0x00000b34,
+       .reo1_aging_thres_ix3 = 0x00000b38,
+
+       /* REO Exception ring address */
+       .reo2_sw0_ring_base = 0x000008c0,
+
+       /* REO Reinject ring address */
+       .sw2reo_ring_base = 0x00000320,
+       .sw2reo1_ring_base = 0x00000398,
+
+       /* REO cmd ring address */
+       .reo_cmd_ring_base = 0x000002a8,
+
+       /* REO status ring address */
+       .reo_status_ring_base = 0x00000aa0,
+
+       /* CE base address */
+       .umac_ce0_src_reg_base = 0x01b80000,
+       .umac_ce0_dest_reg_base = 0x01b81000,
+       .umac_ce1_src_reg_base = 0x01b82000,
+       .umac_ce1_dest_reg_base = 0x01b83000,
+
+       .gcc_gcc_pcie_hot_rst = 0x1e65304,
+};

diff --git a/drivers/net/wireless/ath/ath12k/wifi7/hal_qcc2072.h b/drivers/net/wireless/ath/ath12k/wifi7/hal_qcc2072.h
new file mode 100644 (file)
index 0000000..744d7e0
--- /dev/null
+++ b/drivers/net/wireless/ath/ath12k/wifi7/hal_qcc2072.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: BSD-3-Clause-Clear */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include "../hal.h"
+
+extern const struct ath12k_hw_regs qcc2072_regs;