]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
cpufreq/amd-pstate: Use FIELD_MODIFY()
authorHans Zhang <18255117159@163.com>
Thu, 30 Apr 2026 16:32:12 +0000 (00:32 +0800)
committerViresh Kumar <viresh.kumar@linaro.org>
Tue, 5 May 2026 03:59:21 +0000 (09:29 +0530)
Use FIELD_MODIFY() to remove open-coded bit manipulation.
No functional change intended.

Signed-off-by: Hans Zhang <18255117159@163.com>
Reviewed-by: K Prateek Nayak <kprateek.nayak@amd.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
drivers/cpufreq/amd-pstate.c

index 453084c67327fdf00238683464a38db20f3e4316..1037d17222632f770ee1298219deebbbc841a1ea 100644 (file)
@@ -246,12 +246,10 @@ static int msr_update_perf(struct cpufreq_policy *policy, u8 min_perf,
 
        value = prev = READ_ONCE(cpudata->cppc_req_cached);
 
-       value &= ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK |
-                  AMD_CPPC_DES_PERF_MASK | AMD_CPPC_EPP_PERF_MASK);
-       value |= FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf);
-       value |= FIELD_PREP(AMD_CPPC_DES_PERF_MASK, des_perf);
-       value |= FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf);
-       value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp);
+       FIELD_MODIFY(AMD_CPPC_MAX_PERF_MASK, &value, max_perf);
+       FIELD_MODIFY(AMD_CPPC_DES_PERF_MASK, &value, des_perf);
+       FIELD_MODIFY(AMD_CPPC_MIN_PERF_MASK, &value, min_perf);
+       FIELD_MODIFY(AMD_CPPC_EPP_PERF_MASK, &value, epp);
 
        if (trace_amd_pstate_epp_perf_enabled()) {
                union perf_cached perf = READ_ONCE(cpudata->perf);
@@ -300,8 +298,7 @@ static int msr_set_epp(struct cpufreq_policy *policy, u8 epp)
        int ret;
 
        value = prev = READ_ONCE(cpudata->cppc_req_cached);
-       value &= ~AMD_CPPC_EPP_PERF_MASK;
-       value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp);
+       FIELD_MODIFY(AMD_CPPC_EPP_PERF_MASK, &value, epp);
 
        if (trace_amd_pstate_epp_perf_enabled()) {
                union perf_cached perf = cpudata->perf;
@@ -441,8 +438,7 @@ static int shmem_set_epp(struct cpufreq_policy *policy, u8 epp)
        }
 
        value = READ_ONCE(cpudata->cppc_req_cached);
-       value &= ~AMD_CPPC_EPP_PERF_MASK;
-       value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp);
+       FIELD_MODIFY(AMD_CPPC_EPP_PERF_MASK, &value, epp);
        WRITE_ONCE(cpudata->cppc_req_cached, value);
 
        return ret;
@@ -575,12 +571,10 @@ static int shmem_update_perf(struct cpufreq_policy *policy, u8 min_perf,
 
        value = prev = READ_ONCE(cpudata->cppc_req_cached);
 
-       value &= ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK |
-                  AMD_CPPC_DES_PERF_MASK | AMD_CPPC_EPP_PERF_MASK);
-       value |= FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf);
-       value |= FIELD_PREP(AMD_CPPC_DES_PERF_MASK, des_perf);
-       value |= FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf);
-       value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp);
+       FIELD_MODIFY(AMD_CPPC_MAX_PERF_MASK, &value, max_perf);
+       FIELD_MODIFY(AMD_CPPC_DES_PERF_MASK, &value, des_perf);
+       FIELD_MODIFY(AMD_CPPC_MIN_PERF_MASK, &value, min_perf);
+       FIELD_MODIFY(AMD_CPPC_EPP_PERF_MASK, &value, epp);
 
        if (trace_amd_pstate_epp_perf_enabled()) {
                union perf_cached perf = READ_ONCE(cpudata->perf);