i386.md (*ashl<mode>3_mask): Rewrite as define_insn.

2013-04-01  Wei Mi  <wmi@google.com>

	* config/i386/i386.md (*ashl<mode>3_mask): Rewrite as define_insn.
	Truncate operand 2 using %b asm operand modifier.
	(*<shiftrt_insn><mode>3_mask): Ditto.
	(*<rotate_insn><mode>3_mask): Ditto.

From-SVN: r197313

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index fcae4c401f483859dc0933e7b6557cf556c05cb7..0ad32d9b3bd8368d5401cda08de2e8efa72a651f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2013-04-01  Wei Mi  <wmi@google.com>
+
+       * config/i386/i386.md (*ashl<mode>3_mask): Rewrite as define_insn.
+       Truncate operand 2 using %b asm operand modifier.
+       (*<shiftrt_insn><mode>3_mask): Ditto.
+       (*<rotate_insn><mode>3_mask): Ditto.
+
 2013-04-01  Andrey Belevantsev  <abel@ispras.ru>
 
        Backport from mainline

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 10f383293f4cfa070625329b24daf302b8891350..661dcbc01aff79d5c91a8570c563297b5019e885 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -9257,28 +9257,20 @@
 })
 
 ;; Avoid useless masking of count operand.
-(define_insn_and_split "*ashl<mode>3_mask"
+(define_insn "*ashl<mode>3_mask"
   [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm")
        (ashift:SWI48
          (match_operand:SWI48 1 "nonimmediate_operand" "0")
          (subreg:QI
            (and:SI
-             (match_operand:SI 2 "nonimmediate_operand" "c")
+             (match_operand:SI 2 "register_operand" "c")
              (match_operand:SI 3 "const_int_operand" "n")) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands)
    && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
       == GET_MODE_BITSIZE (<MODE>mode)-1"
-  "#"
-  "&& 1"
-  [(parallel [(set (match_dup 0)
-                  (ashift:SWI48 (match_dup 1) (match_dup 2)))
-             (clobber (reg:CC FLAGS_REG))])]
 {
-  if (can_create_pseudo_p ())
-    operands [2] = force_reg (SImode, operands[2]);
-
-  operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0);
+  return "sal{<imodesuffix>}\t{%b2, %0|%0, %b2}";
 }
   [(set_attr "type" "ishift")
    (set_attr "mode" "<MODE>")])
@@ -9822,28 +9814,20 @@
   "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
 
 ;; Avoid useless masking of count operand.
-(define_insn_and_split "*<shiftrt_insn><mode>3_mask"
+(define_insn "*<shiftrt_insn><mode>3_mask"
   [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm")
        (any_shiftrt:SWI48
          (match_operand:SWI48 1 "nonimmediate_operand" "0")
          (subreg:QI
            (and:SI
-             (match_operand:SI 2 "nonimmediate_operand" "c")
+             (match_operand:SI 2 "register_operand" "c")
              (match_operand:SI 3 "const_int_operand" "n")) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
    && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
       == GET_MODE_BITSIZE (<MODE>mode)-1"
-  "#"
-  "&& 1"
-  [(parallel [(set (match_dup 0)
-                  (any_shiftrt:SWI48 (match_dup 1) (match_dup 2)))
-             (clobber (reg:CC FLAGS_REG))])]
 {
-  if (can_create_pseudo_p ())
-    operands [2] = force_reg (SImode, operands[2]);
-
-  operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0);
+  return "<shift>{<imodesuffix>}\t{%b2, %0|%0, %b2}";
 }
   [(set_attr "type" "ishift")
    (set_attr "mode" "<MODE>")])
@@ -10202,28 +10186,20 @@
   "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
 
 ;; Avoid useless masking of count operand.
-(define_insn_and_split "*<rotate_insn><mode>3_mask"
+(define_insn "*<rotate_insn><mode>3_mask"
   [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm")
        (any_rotate:SWI48
          (match_operand:SWI48 1 "nonimmediate_operand" "0")
          (subreg:QI
            (and:SI
-             (match_operand:SI 2 "nonimmediate_operand" "c")
+             (match_operand:SI 2 "register_operand" "c")
              (match_operand:SI 3 "const_int_operand" "n")) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
    && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
       == GET_MODE_BITSIZE (<MODE>mode)-1"
-  "#"
-  "&& 1"
-  [(parallel [(set (match_dup 0)
-                  (any_rotate:SWI48 (match_dup 1) (match_dup 2)))
-             (clobber (reg:CC FLAGS_REG))])]
 {
-  if (can_create_pseudo_p ())
-    operands [2] = force_reg (SImode, operands[2]);
-
-  operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0);
+  return "<rotate>{<imodesuffix>}\t{%b2, %0|%0, %b2}";
 }
   [(set_attr "type" "rotate")
    (set_attr "mode" "<MODE>")])