str w2, [x1]
ldr w0, =0xfa50392f // CPU hotplug magic
-#if defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_A133)
+#if defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_A133) || \
+ defined(CONFIG_MACH_SUN55I_A523)
ldr w2, =(SUNXI_R_CPUCFG_BASE + 0x1c0)
str w0, [x2], #0x4
-#elif CONFIG_MACH_SUN50I_H6
+#elif defined(CONFIG_MACH_SUN50I_H6)
ldr w2, =(SUNXI_RTC_BASE + 0x1b8) // BOOT_CPU_HP_FLAG_REG
str w0, [x2], #0x4
#else
config SUNXI_SRAM_ADDRESS
hex
default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
+ default 0x44000 if MACH_SUN55I_A523
default 0x20000 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2
default 0x0
---help---
hex
depends on ARM64
default 0x08100040 if MACH_SUN50I_A133
+ default 0x08000040 if MACH_SUN55I_A523
default 0x09010040 if SUN50I_GEN_H6
default 0x017000a0
---help---
default 0x00044000 if MACH_SUN50I || MACH_SUN50I_H5
default 0x40000000 if MACH_SUN50I_H616
default 0x00104000 if SUN50I_GEN_H6
+ default 0x00054000 if MACH_SUN55I_A523
default 0x0
help
Address where BL31 (TF-A) is loaded, or zero if BL31 is not used.
# TODO: try out A80's 8GiB DRAM space
config SUNXI_DRAM_MAX_SIZE
hex
- default 0x100000000 if MACH_SUN50I_H616 || MACH_SUN50I_A133
+ default 0x100000000 if MACH_SUN50I_H616 || MACH_SUN50I_A133 || MACH_SUN55I_A523
default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
default 0x80000000
select SUN50I_GEN_H6
imply OF_UPSTREAM
+config MACH_SUN55I_A523
+ bool "sun55i (Allwinner A523/A527/T527/H728)"
+ select ARM64
+ select SUNXI_GEN_NCAT2
+ select SUNXI_NEW_PINCTRL
+ select DRAM_SUN55I_A523
+ select FIT
+ select SPL_LOAD_FIT if SPL
+ imply OF_UPSTREAM
+
endchoice
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
config DRAM_ZQ
int "sunxi dram zq value"
- depends on !MACH_SUN50I_H616 && !MACH_SUN50I_A133
+ depends on !MACH_SUN50I_H616
+ depends on !MACH_SUN50I_A133
+ depends on !MACH_SUN55I_A523
default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \
MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
default 127 if MACH_SUN7I
config DRAM_ODT_EN
bool "sunxi dram odt enable"
depends on !MACH_SUN50I_H616
+ depends on !MACH_SUN55I_A523
default y if MACH_SUN8I_A23
default y if MACH_SUNXI_H3_H5
default y if MACH_SUN8I_R40
config SYS_CLK_FREQ
default 408000000 if MACH_SUNIV
+ default 792000000 if MACH_SUN55I_A523
default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
default 888000000 if MACH_SUN50I_H6
default 912000000 if MACH_SUN7I
default "sun50i" if MACH_SUN50I_H6
default "sun50i" if MACH_SUN50I_H616
default "sun50i" if MACH_SUN50I_A133
+ default "sun55i" if MACH_SUN55I_A523
config SYS_BOARD
default "sunxi"
---help---
See I2C0_ENABLE help text.
-if SUNXI_GEN_SUN6I || SUN50I_GEN_H6
+if SUNXI_GEN_SUN6I || SUN50I_GEN_H6 || SUNXI_GEN_NCAT2
config R_I2C_ENABLE
bool "Enable the PRCM I2C/TWI controller"
# This is used for the pmic on H3
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_H616_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN50I_H616_GPH_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN55I_A523)
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(9), 2);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(10), 2);
+ sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
IS_ENABLED(CONFIG_SUN50I_GEN_NCAT2)) {
val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
+ /* TODO: A523: keep only the lower two bits? */
writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
}
if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) {
puts("CPU: Allwinner H616 (SUN50I)\n");
#elif defined CONFIG_MACH_SUN50I_A133
puts("CPU: Allwinner A133 (SUN50I)\n");
+#elif defined CONFIG_MACH_SUN55I_A523
+ puts("CPU: Allwinner A523 (SUN55I)\n");
#else
#warning Please update cpu_info.c with correct CPU information
puts("CPU: SUNXI Family\n");
clock_twi_onoff(5, 1);
sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI);
sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI);
+#elif CONFIG_MACH_SUN55I_A523
+ clock_twi_onoff(5, 1);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_GPL_R_TWI);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_GPL_R_TWI);
#else
clock_twi_onoff(5, 1);
sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
-#elif defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_A133)
+#elif defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_A133) || \
+ defined(CONFIG_MACH_SUN55I_A523)
/* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */
for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(16); pin++) {
if (pin > SUNXI_GPC(1) && pin < SUNXI_GPC(5))
default 0x1b000 if AM33XX && !TI_SECURE_DEVICE
default 0xec00 if OMAP34XX
default 0x10000 if ARCH_MX6 && !MX6_OCRAM_256KB
- default 0xbfa0 if MACH_SUN50I_H616 || MACH_SUN50I_A133
+ default 0xbfa0 if MACH_SUN50I_H616 || MACH_SUN50I_A133 || MACH_SUN55I_A523
default 0x7000 if RCAR_GEN3
default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0
default 0x7fa0 if ARCH_SUNXI
default 0x00912000 if ARCH_MX7
default 0x40301350 if OMAP54XX
default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I
+ default 0x44060 if MACH_SUN55I_A523
default 0x20060 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2
default 0x00060 if ARCH_SUNXI
default 0xfffc0000 if ARCH_ZYNQMP
default 0x118000 if MACH_SUN50I_H6
default 0x52a00 if MACH_SUN50I_H616
default 0x40000 if MACH_SUN8I_R528 || MACH_SUN50I_A133
+ default 0x44000 if MACH_SUN55I_A523
default 0x54000 if MACH_SUN50I || MACH_SUN50I_H5
default 0x18000 if MACH_SUN9I
default 0x8000 if ARCH_SUNXI
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Placeholder wrapper to allow addressing Allwinner devices with Cortex-A55
+ * cores separately. Please do not add anything in here.
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */