arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe

The RZ Smarc Carrier-II board has PCIe slots mounted on it.
Enable PCIe support.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260318085119.44717-5-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 30ffd458f188b944f68f3a75a0c6f6946d651f56..9be57785d9d59da9fd86bf66305a08e0be1b53a0 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -122,6 +122,11 @@
 #endif
 };
 
+&pcie {
+       pinctrl-0 = <&pcie_pins>;
+       pinctrl-names = "default";
+};
+
 &pinctrl {
        canfd_pins: canfd {
                can1_pins: can1 {
@@ -145,6 +150,17 @@
                input-schmitt-enable;
        };
 
+       pcie-clkreq-n-hog {
+               gpio-hog;
+               gpios = <RZG3E_GPIO(4, 5) GPIO_ACTIVE_HIGH>;
+               output-low;
+               line-name = "PCIE_M2B_CKREQ";
+       };
+
+       pcie_pins: pcie {
+               pinmux = <RZG3E_PORT_PINMUX(G, 7, 1)>; /* PCIE_RST_OUT# */
+       };
+
        rsci2_pins: rsci2 {
                pinmux = <RZG3E_PORT_PINMUX(1, 0, 1)>, /* RXD2 */
                         <RZG3E_PORT_PINMUX(1, 1, 1)>, /* TXD2 */

diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
index b607b5d6c259e6becffb14fc9092ef51129925e4..e2a34577a1a1b3afcc542ecb07123d1ebbfdc321 100644 (file)
--- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
+++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
@@ -96,6 +96,10 @@
        clock-frequency = <400000>;
 };
 
+&pcie {
+       status = "okay";
+};
+
 &scif0 {
        status = "okay";
 };