realtek: 6.12: fix phy-mode for XGS1250-12 port 1-8

Per IEEE 802.3 definition we have:
- parallel XGMII for single 10GBit ONLY links
- serial USGMII for 8 port 1GBit links (not known by kernel)
- serial USXGMII: for single/multiple links with a total bandwidth of 10GBit

The phy-mode of the first eight ports of the XGS1250-12 have always been
defined as XGMII (without S). This came from a confusion with the similar
named Realtek proprietary XSGMII (with S) mode that is basically 10GB SGMII.
From the above definition this is wrong but worked until kernel 6.6. With
the upgrade to 6.12 there is an enforced capabilities check within
phy_caps_from_interface() and link validation fails with

lan1: validation of xgmii with support 62ef and advertisement 62c0 failed: -EINVAL
lan1: failed to connect to PHY: -EINVAL
lan1: error -22 setting up PHY for tree 0, switch 0, port 0

Switch the ports to USXGMII as the most flexible option. This might be no
final solution but at least it better describes the phy/mac link.

Fixes 5b8b382df9a960d88 ("realtek: Add support for ZxXEL XGS1250-12 Switch")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>

diff --git a/target/linux/realtek/dts/rtl9302_zyxel_xgs1250-12.dts b/target/linux/realtek/dts/rtl9302_zyxel_xgs1250-12.dts
index aa485113725fa2c8b5383313ef9ae1c77b135df1..182047e608737a04d80582142ca2d5a3a749f2e4 100644 (file)
--- a/target/linux/realtek/dts/rtl9302_zyxel_xgs1250-12.dts
+++ b/target/linux/realtek/dts/rtl9302_zyxel_xgs1250-12.dts
@@ -325,56 +325,56 @@
                        reg = <0>;
                        label = "lan1";
                        phy-handle = <&phy0>;
-                       phy-mode = "xgmii";
+                       phy-mode = "usxgmii";
                        led-set = <0>;
                };
                port@1 {
                        reg = <1>;
                        label = "lan2";
                        phy-handle = <&phy1>;
-                       phy-mode = "xgmii";
+                       phy-mode = "usxgmii";
                        led-set = <0>;
                };
                port@2 {
                        reg = <2>;
                        label = "lan3";
                        phy-handle = <&phy2>;
-                       phy-mode = "xgmii";
+                       phy-mode = "usxgmii";
                        led-set = <0>;
                };
                port@3 {
                        reg = <3>;
                        label = "lan4";
                        phy-handle = <&phy3>;
-                       phy-mode = "xgmii";
+                       phy-mode = "usxgmii";
                        led-set = <0>;
                };
                port@4 {
                        reg = <4>;
                        label = "lan5";
                        phy-handle = <&phy4>;
-                       phy-mode = "xgmii";
+                       phy-mode = "usxgmii";
                        led-set = <0>;
                };
                port@5 {
                        reg = <5>;
                        label = "lan6";
                        phy-handle = <&phy5>;
-                       phy-mode = "xgmii";
+                       phy-mode = "usxgmii";
                        led-set = <0>;
                };
                port@6 {
                        reg = <6>;
                        label = "lan7";
                        phy-handle = <&phy6>;
-                       phy-mode = "xgmii";
+                       phy-mode = "usxgmii";
                        led-set = <0>;
                };
                port@7 {
                        reg = <7>;
                        label = "lan8";
                        phy-handle = <&phy7>;
-                       phy-mode = "xgmii";
+                       phy-mode = "usxgmii";
                        led-set = <0>;
                };