arm64: dts: freescale: imx8mp-verdin: Split UART_2 pinctrl group

Some carrier board reuse the UART_2 control signals as GPIO, split
the pinctrl RTS/CTS in separated nodes to maximize flexibility.

Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
index d31f8082394fd3ab995ad25c230d8f62fc247c28..9fee2cf9ef5461b111406591f3c571e6c458561e 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
@@ -846,7 +846,7 @@
 /* Verdin UART_2 */
 &uart2 {
        pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart2>;
+       pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart2_cts>, <&pinctrl_uart2_rts>;
        uart-has-rtscts;
 };
 
@@ -1277,10 +1277,18 @@
                        <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX           0x1c4>; /* SODIMM 131 */
        };
 
+       pinctrl_uart2_cts: uart2ctsgrp {
+               fsl,pins =
+                       <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS          0x1c4>; /* SODIMM 143 */
+       };
+
+       pinctrl_uart2_rts: uart2rtsgrp {
+               fsl,pins =
+                       <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS          0x1c4>; /* SODIMM 141 */
+       };
+
        pinctrl_uart2: uart2grp {
                fsl,pins =
-                       <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS          0x1c4>, /* SODIMM 143 */
-                       <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS          0x1c4>, /* SODIMM 141 */
                        <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX           0x1c4>, /* SODIMM 137 */
                        <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX           0x1c4>; /* SODIMM 139 */
        };