lscpu: riscv: preserve ISA extension order

The Linux RISC-V UABI defines the canonical ISA string order in /proc/cpuinfo. Do not sort multi-letter extensions alphabetically in lscpu; keep the kernel-provided order and only replace separators for display.

diff --git a/sys-utils/lscpu-riscv.c b/sys-utils/lscpu-riscv.c
index 3d017620643135ad90334450d8ca5a8a6b6910b3..f49aa3be48ce49f90a9f5e045c1a9a44d9160c20 100644 (file)
--- a/sys-utils/lscpu-riscv.c
+++ b/sys-utils/lscpu-riscv.c
@@ -14,11 +14,6 @@
 #include "strv.h"
 #include "cctype.h"
 
-static int riscv_cmp_func(const void *a, const void *b)
-{
-       return strcmp(*(const char **)a, *(const char **)b);
-}
-
 bool is_riscv(struct lscpu_cputype *ct)
 {
        const char *base_isa[] = {"rv32", "rv64", "rv128"};
@@ -42,11 +37,7 @@ void lscpu_format_isa_riscv(struct lscpu_cputype *ct)
 
        split = ul_strv_split(ct->isa, "_");
 
-       /* Sort multi-letter extensions alphabetically */
-       if (ul_strv_length(split) > 1)
-               qsort(&split[1], ul_strv_length(split) - 1, sizeof(char *), riscv_cmp_func);
-
-       /* Keep Base ISA and single-letter extensions at the start */
+       /* Keep the kernel-provided ISA extension order. */
        strcpy(ct->isa, split[0]);
 
        for (i = 1; i < ul_strv_length(split); i++) {

diff --git a/tests/expected/lscpu/lscpu-rv64-visionfive2 b/tests/expected/lscpu/lscpu-rv64-visionfive2
index 762d7216be7be6f0084b70ea190792eec6f2e580..8997a1769ea84bcffb0eb68b83b85275f2e1c5fc 100644 (file)
--- a/tests/expected/lscpu/lscpu-rv64-visionfive2
+++ b/tests/expected/lscpu/lscpu-rv64-visionfive2
@@ -8,7 +8,7 @@ Model:               0x4210427
 Thread(s) per core:  1
 Core(s) per socket:  4
 Socket(s):           1
-ISA:                 rv64imafdc zba zbb zicntr zicsr zifencei zihpm
+ISA:                 rv64imafdc zicntr zicsr zifencei zihpm zba zbb
 MMU:                 sv39
 L1d cache:           128 KiB (4 instances)
 L1i cache:           128 KiB (4 instances)