PCI: dwc: Use common pci_host_common_link_train_delay() helper

The DWC driver already implements the 100 ms delay required by PCIe
r6.0 sec 6.6.1 by checking pci->max_link_speed and calling msleep(100).

Replace the open-coded msleep() with the new common helper
pci_host_common_link_train_delay() to reduce code duplication and
improve maintainability. No functional change intended.

Signed-off-by: Hans Zhang <18255117159@163.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260518004246.1384532-5-18255117159@163.com

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index c11cf61b8319e66ca5b50915ffd1cc9691d54974..7021d21bb6011ec2fcb18e1230bb87c5fbb1fc1f 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -22,6 +22,7 @@
 #include <linux/sizes.h>
 #include <linux/types.h>
 
+#include "../pci-host-common.h"
 #include "../../pci.h"
 #include "pcie-designware.h"
 
@@ -799,13 +800,7 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci)
                return -ETIMEDOUT;
        }
 
-       /*
-        * As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link
-        * speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms
-        * after Link training completes before sending a Configuration Request.
-        */
-       if (pci->max_link_speed > 2)
-               msleep(PCIE_RESET_CONFIG_WAIT_MS);
+       pci_host_common_link_train_delay(pci->max_link_speed);
 
        offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
        val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);