]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
wifi: rtw89: phy: support EDCCA log per PHY
authorPing-Ke Shih <pkshih@realtek.com>
Fri, 17 Jan 2025 07:28:27 +0000 (15:28 +0800)
committerPing-Ke Shih <pkshih@realtek.com>
Mon, 3 Feb 2025 01:55:20 +0000 (09:55 +0800)
The registers of EDCCA log for PHY 1 isn't a simple offset, so define
them accordingly. Then the function use register set to access reports
according to phy_idx.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20250117072828.16728-8-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/core.h
drivers/net/wireless/realtek/rtw89/phy.c
drivers/net/wireless/realtek/rtw89/reg.h
drivers/net/wireless/realtek/rtw89/rtw8851b.c
drivers/net/wireless/realtek/rtw89/rtw8852a.c
drivers/net/wireless/realtek/rtw89/rtw8852b.c
drivers/net/wireless/realtek/rtw89/rtw8852bt.c
drivers/net/wireless/realtek/rtw89/rtw8852c.c
drivers/net/wireless/realtek/rtw89/rtw8922a.c

index c8b4809c2f3680832824dfbfeb7e1d7cc8ae5088..970730291e567991e5a56cb0d4609de44ef4b8db 100644 (file)
@@ -4190,10 +4190,12 @@ struct rtw89_edcca_regs {
        u32 edcca_p_mask;
        u32 ppdu_level;
        u32 ppdu_mask;
-       u32 rpt_a;
-       u32 rpt_b;
-       u32 rpt_sel;
-       u32 rpt_sel_mask;
+       struct rtw89_edcca_p_regs {
+               u32 rpt_a;
+               u32 rpt_b;
+               u32 rpt_sel;
+               u32 rpt_sel_mask;
+       } p[RTW89_PHY_NUM];
        u32 rpt_sel_be;
        u32 rpt_sel_be_mask;
        u32 tx_collision_t2r_st;
index f1029da4a78eaeb265e7313caf0291536b262671..a5299295b7774937197bc64c7980ea76352181dd 100644 (file)
@@ -7017,6 +7017,7 @@ void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev,
 static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
 {
        const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
+       const struct rtw89_edcca_p_regs *edcca_p_regs;
        bool flag_fb, flag_p20, flag_s20, flag_s40, flag_s80;
        s8 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80;
        u8 path, per20_bitmap;
@@ -7026,13 +7027,18 @@ static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *b
        if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_EDCCA))
                return;
 
+       if (bb->phy_idx == RTW89_PHY_1)
+               edcca_p_regs = &edcca_regs->p[RTW89_PHY_1];
+       else
+               edcca_p_regs = &edcca_regs->p[RTW89_PHY_0];
+
        if (rtwdev->chip->chip_id == RTL8922A)
                rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
                                       edcca_regs->rpt_sel_be_mask, 0);
 
-       rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
-                              edcca_regs->rpt_sel_mask, 0);
-       tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b);
+       rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
+                              edcca_p_regs->rpt_sel_mask, 0);
+       tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b);
        path = u32_get_bits(tmp, B_EDCCA_RPT_B_PATH_MASK);
        flag_s80 = u32_get_bits(tmp, B_EDCCA_RPT_B_S80);
        flag_s40 = u32_get_bits(tmp, B_EDCCA_RPT_B_S40);
@@ -7043,19 +7049,19 @@ static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *b
        pwdb_p20 = u32_get_bits(tmp, MASKBYTE2);
        pwdb_fb = u32_get_bits(tmp, MASKBYTE3);
 
-       rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
-                              edcca_regs->rpt_sel_mask, 4);
-       tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b);
+       rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
+                              edcca_p_regs->rpt_sel_mask, 4);
+       tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b);
        pwdb_s80 = u32_get_bits(tmp, MASKBYTE1);
        pwdb_s40 = u32_get_bits(tmp, MASKBYTE2);
 
-       per20_bitmap = rtw89_phy_read32_mask(rtwdev, edcca_regs->rpt_a,
+       per20_bitmap = rtw89_phy_read32_mask(rtwdev, edcca_p_regs->rpt_a,
                                             MASKBYTE0);
 
        if (rtwdev->chip->chip_id == RTL8922A) {
                rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
                                       edcca_regs->rpt_sel_be_mask, 4);
-               tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b);
+               tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b);
                pwdb[0] = u32_get_bits(tmp, MASKBYTE3);
                pwdb[1] = u32_get_bits(tmp, MASKBYTE2);
                pwdb[2] = u32_get_bits(tmp, MASKBYTE1);
@@ -7063,33 +7069,33 @@ static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *b
 
                rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
                                       edcca_regs->rpt_sel_be_mask, 5);
-               tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b);
+               tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b);
                pwdb[4] = u32_get_bits(tmp, MASKBYTE3);
                pwdb[5] = u32_get_bits(tmp, MASKBYTE2);
                pwdb[6] = u32_get_bits(tmp, MASKBYTE1);
                pwdb[7] = u32_get_bits(tmp, MASKBYTE0);
        } else {
-               rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
-                                      edcca_regs->rpt_sel_mask, 0);
-               tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a);
+               rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
+                                      edcca_p_regs->rpt_sel_mask, 0);
+               tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a);
                pwdb[0] = u32_get_bits(tmp, MASKBYTE3);
                pwdb[1] = u32_get_bits(tmp, MASKBYTE2);
 
-               rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
-                                      edcca_regs->rpt_sel_mask, 1);
-               tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a);
+               rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
+                                      edcca_p_regs->rpt_sel_mask, 1);
+               tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a);
                pwdb[2] = u32_get_bits(tmp, MASKBYTE3);
                pwdb[3] = u32_get_bits(tmp, MASKBYTE2);
 
-               rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
-                                      edcca_regs->rpt_sel_mask, 2);
-               tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a);
+               rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
+                                      edcca_p_regs->rpt_sel_mask, 2);
+               tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a);
                pwdb[4] = u32_get_bits(tmp, MASKBYTE3);
                pwdb[5] = u32_get_bits(tmp, MASKBYTE2);
 
-               rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
-                                      edcca_regs->rpt_sel_mask, 3);
-               tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a);
+               rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
+                                      edcca_p_regs->rpt_sel_mask, 3);
+               tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a);
                pwdb[6] = u32_get_bits(tmp, MASKBYTE3);
                pwdb[7] = u32_get_bits(tmp, MASKBYTE2);
        }
index 10d0efa7a58efd7313faadbf7cb2d30bbb45f4cb..c992835d4b63cc8b00bb7e53e2291363b5dc0b43 100644 (file)
 #define B_EDCCA_RPT_B_S40 BIT(4)
 #define B_EDCCA_RPT_B_S80 BIT(3)
 #define B_EDCCA_RPT_B_PATH_MASK GENMASK(2, 1)
+#define R_EDCCA_RPT_P1_A 0x1740
+#define R_EDCCA_RPT_P1_B 0x1744
 #define R_SWSI_V1 0x174C
 #define B_SWSI_W_BUSY_V1 BIT(24)
 #define B_SWSI_R_BUSY_V1 BIT(25)
 #define B_TXCKEN_FORCE_ALL GENMASK(24, 0)
 #define R_EDCCA_RPT_SEL 0x20CC
 #define B_EDCCA_RPT_SEL_MSK GENMASK(2, 0)
+#define B_EDCCA_RPT_SEL_P1_MSK GENMASK(5, 3)
 #define R_ADC_FIFO 0x20fc
 #define B_ADC_FIFO_RST GENMASK(31, 24)
 #define B_ADC_FIFO_RXK GENMASK(31, 16)
 #define B_P1_EN_SOUND_WO_NDP BIT(1)
 #define R_EDCCA_RPT_A_BE 0x2E38
 #define R_EDCCA_RPT_B_BE 0x2E3C
+#define R_EDCCA_RPT_P1_A_BE 0x2E40
+#define R_EDCCA_RPT_P1_B_BE 0x2E44
 #define R_S1_HW_SI_DIS 0x3200
 #define B_S1_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
 #define R_P1_RXCK 0x32A0
index 0487d1cbe60576c79531e43c45933ae7aff2af8d..82289dbad1f4da37869c464d99a904f6869f461e 100644 (file)
@@ -224,10 +224,17 @@ static const struct rtw89_edcca_regs rtw8851b_edcca_regs = {
        .edcca_p_mask                   = B_EDCCA_LVL_MSK1,
        .ppdu_level                     = R_SEG0R_EDCCA_LVL_V1,
        .ppdu_mask                      = B_EDCCA_LVL_MSK3,
-       .rpt_a                          = R_EDCCA_RPT_A,
-       .rpt_b                          = R_EDCCA_RPT_B,
-       .rpt_sel                        = R_EDCCA_RPT_SEL,
-       .rpt_sel_mask                   = B_EDCCA_RPT_SEL_MSK,
+       .p = {{
+               .rpt_a                  = R_EDCCA_RPT_A,
+               .rpt_b                  = R_EDCCA_RPT_B,
+               .rpt_sel                = R_EDCCA_RPT_SEL,
+               .rpt_sel_mask           = B_EDCCA_RPT_SEL_MSK,
+       }, {
+               .rpt_a                  = R_EDCCA_RPT_P1_A,
+               .rpt_b                  = R_EDCCA_RPT_P1_B,
+               .rpt_sel                = R_EDCCA_RPT_SEL,
+               .rpt_sel_mask           = B_EDCCA_RPT_SEL_P1_MSK,
+       }},
        .tx_collision_t2r_st            = R_TX_COLLISION_T2R_ST,
        .tx_collision_t2r_st_mask       = B_TX_COLLISION_T2R_ST_M,
 };
index 8a9a5201b2ee6395882e065e42cb9dea4ff31c2a..2046832d021fdd99ab7417de7a7f2f96fbb15482 100644 (file)
@@ -522,10 +522,17 @@ static const struct rtw89_edcca_regs rtw8852a_edcca_regs = {
        .edcca_p_mask                   = B_EDCCA_LVL_MSK1,
        .ppdu_level                     = R_SEG0R_EDCCA_LVL,
        .ppdu_mask                      = B_EDCCA_LVL_MSK3,
-       .rpt_a                          = R_EDCCA_RPT_A,
-       .rpt_b                          = R_EDCCA_RPT_B,
-       .rpt_sel                        = R_EDCCA_RPT_SEL,
-       .rpt_sel_mask                   = B_EDCCA_RPT_SEL_MSK,
+       .p = {{
+               .rpt_a                  = R_EDCCA_RPT_A,
+               .rpt_b                  = R_EDCCA_RPT_B,
+               .rpt_sel                = R_EDCCA_RPT_SEL,
+               .rpt_sel_mask           = B_EDCCA_RPT_SEL_MSK,
+       }, {
+               .rpt_a                  = R_EDCCA_RPT_P1_A,
+               .rpt_b                  = R_EDCCA_RPT_P1_B,
+               .rpt_sel                = R_EDCCA_RPT_SEL,
+               .rpt_sel_mask           = B_EDCCA_RPT_SEL_P1_MSK,
+       }},
        .tx_collision_t2r_st            = R_TX_COLLISION_T2R_ST,
        .tx_collision_t2r_st_mask       = B_TX_COLLISION_T2R_ST_M,
 };
index cbaf54f88af6fc9f0e24f6d5d6b593c7e808ccbd..652914a362451e9ffe24faa8cd22d7f8984711c4 100644 (file)
@@ -189,10 +189,17 @@ static const struct rtw89_edcca_regs rtw8852b_edcca_regs = {
        .edcca_p_mask                   = B_EDCCA_LVL_MSK1,
        .ppdu_level                     = R_SEG0R_EDCCA_LVL_V1,
        .ppdu_mask                      = B_EDCCA_LVL_MSK3,
-       .rpt_a                          = R_EDCCA_RPT_A,
-       .rpt_b                          = R_EDCCA_RPT_B,
-       .rpt_sel                        = R_EDCCA_RPT_SEL,
-       .rpt_sel_mask                   = B_EDCCA_RPT_SEL_MSK,
+       .p = {{
+               .rpt_a                  = R_EDCCA_RPT_A,
+               .rpt_b                  = R_EDCCA_RPT_B,
+               .rpt_sel                = R_EDCCA_RPT_SEL,
+               .rpt_sel_mask           = B_EDCCA_RPT_SEL_MSK,
+       }, {
+               .rpt_a                  = R_EDCCA_RPT_P1_A,
+               .rpt_b                  = R_EDCCA_RPT_P1_B,
+               .rpt_sel                = R_EDCCA_RPT_SEL,
+               .rpt_sel_mask           = B_EDCCA_RPT_SEL_P1_MSK,
+       }},
        .tx_collision_t2r_st            = R_TX_COLLISION_T2R_ST,
        .tx_collision_t2r_st_mask       = B_TX_COLLISION_T2R_ST_M,
 };
index c0ae5dca30492a25792f0a15aad4c4ef6838aa48..6f15245b2f74967193bafb6f2bdc03ebb370e89b 100644 (file)
@@ -187,10 +187,17 @@ static const struct rtw89_edcca_regs rtw8852bt_edcca_regs = {
        .edcca_p_mask                   = B_EDCCA_LVL_MSK1,
        .ppdu_level                     = R_SEG0R_EDCCA_LVL_V1,
        .ppdu_mask                      = B_EDCCA_LVL_MSK3,
-       .rpt_a                          = R_EDCCA_RPT_A,
-       .rpt_b                          = R_EDCCA_RPT_B,
-       .rpt_sel                        = R_EDCCA_RPT_SEL,
-       .rpt_sel_mask                   = B_EDCCA_RPT_SEL_MSK,
+       .p = {{
+               .rpt_a                  = R_EDCCA_RPT_A,
+               .rpt_b                  = R_EDCCA_RPT_B,
+               .rpt_sel                = R_EDCCA_RPT_SEL,
+               .rpt_sel_mask           = B_EDCCA_RPT_SEL_MSK,
+       }, {
+               .rpt_a                  = R_EDCCA_RPT_P1_A,
+               .rpt_b                  = R_EDCCA_RPT_P1_B,
+               .rpt_sel                = R_EDCCA_RPT_SEL,
+               .rpt_sel_mask           = B_EDCCA_RPT_SEL_P1_MSK,
+       }},
        .tx_collision_t2r_st            = R_TX_COLLISION_T2R_ST,
        .tx_collision_t2r_st_mask       = B_TX_COLLISION_T2R_ST_M,
 };
index 106df618bb588cfc6c76d0d3301b371b9e98b75e..ecc1ff358583158d32aa7d3ecb7a2a5aeaccc9d5 100644 (file)
@@ -186,10 +186,17 @@ static const struct rtw89_edcca_regs rtw8852c_edcca_regs = {
        .edcca_p_mask                   = B_EDCCA_LVL_MSK1,
        .ppdu_level                     = R_SEG0R_EDCCA_LVL,
        .ppdu_mask                      = B_EDCCA_LVL_MSK3,
-       .rpt_a                          = R_EDCCA_RPT_A,
-       .rpt_b                          = R_EDCCA_RPT_B,
-       .rpt_sel                        = R_EDCCA_RPT_SEL,
-       .rpt_sel_mask                   = B_EDCCA_RPT_SEL_MSK,
+       .p = {{
+               .rpt_a                  = R_EDCCA_RPT_A,
+               .rpt_b                  = R_EDCCA_RPT_B,
+               .rpt_sel                = R_EDCCA_RPT_SEL,
+               .rpt_sel_mask           = B_EDCCA_RPT_SEL_MSK,
+       }, {
+               .rpt_a                  = R_EDCCA_RPT_P1_A,
+               .rpt_b                  = R_EDCCA_RPT_P1_B,
+               .rpt_sel                = R_EDCCA_RPT_SEL,
+               .rpt_sel_mask           = B_EDCCA_RPT_SEL_P1_MSK,
+       }},
        .tx_collision_t2r_st            = R_TX_COLLISION_T2R_ST,
        .tx_collision_t2r_st_mask       = B_TX_COLLISION_T2R_ST_M,
 };
index 11d66bfceb15f135a5b2c63b670cf60e0a5af841..898a65a721dc4f7f5adefcb60399f04e97ee3041 100644 (file)
@@ -205,10 +205,17 @@ static const struct rtw89_edcca_regs rtw8922a_edcca_regs = {
        .edcca_p_mask                   = B_EDCCA_LVL_MSK1,
        .ppdu_level                     = R_SEG0R_PPDU_LVL_BE,
        .ppdu_mask                      = B_EDCCA_LVL_MSK1,
-       .rpt_a                          = R_EDCCA_RPT_A_BE,
-       .rpt_b                          = R_EDCCA_RPT_B_BE,
-       .rpt_sel                        = R_EDCCA_RPT_SEL_BE,
-       .rpt_sel_mask                   = B_EDCCA_RPT_SEL_MSK,
+       .p = {{
+               .rpt_a                  = R_EDCCA_RPT_A_BE,
+               .rpt_b                  = R_EDCCA_RPT_B_BE,
+               .rpt_sel                = R_EDCCA_RPT_SEL_BE,
+               .rpt_sel_mask           = B_EDCCA_RPT_SEL_MSK,
+       }, {
+               .rpt_a                  = R_EDCCA_RPT_P1_A_BE,
+               .rpt_b                  = R_EDCCA_RPT_P1_B_BE,
+               .rpt_sel                = R_EDCCA_RPT_SEL_BE,
+               .rpt_sel_mask           = B_EDCCA_RPT_SEL_P1_MSK,
+       }},
        .rpt_sel_be                     = R_EDCCA_RPTREG_SEL_BE,
        .rpt_sel_be_mask                = B_EDCCA_RPTREG_SEL_BE_MSK,
        .tx_collision_t2r_st            = R_TX_COLLISION_T2R_ST_BE,