RISC-V: Fix regression

Due to recent middle-end loop vectorizer changes, these tests have regression and
the changes are reasonable. Adapt test to fix the regression.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Adapt test.
	* gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/mod-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/shift-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/shift-2.c: Ditto.

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
index befa4b85e8fb58a9e3d8362e760e78a1dd905aa5..d5348855aa03bf1dc722e0c6192c40b92e135b64 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
@@ -4,5 +4,5 @@
 #include "shift-template.h"
 
 /* { dg-final { scan-assembler-times {\tvsll\.vv} 8 } } */
-/* { dg-final { scan-assembler-times {\tvsrl\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvsrl\.vv} 2 } } */
 /* { dg-final { scan-assembler-times {\tvsra\.vv} 4 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
index 976b29fa356508021b803ef0dc0618d9bbff0714..a533dc79bc09bddf1b04b04d1804e8ca482d7828 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
@@ -4,5 +4,5 @@
 #include "shift-template.h"
 
 /* { dg-final { scan-assembler-times {\tvsll\.vv} 8 } } */
-/* { dg-final { scan-assembler-times {\tvsrl\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvsrl\.vv} 2 } } */
 /* { dg-final { scan-assembler-times {\tvsra\.vv} 4 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c
index 57bbf8fbc683c6397c44a63d14cce3f843af45e7..17d2784b90dcb70b56df36fe59d0401a873ed167 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c
@@ -53,5 +53,5 @@ DEF_OP_VV (mod, 128, int64_t, %)
 DEF_OP_VV (mod, 256, int64_t, %)
 DEF_OP_VV (mod, 512, int64_t, %)
 
-/* { dg-final { scan-assembler-times {vremu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
+/* { dg-final { scan-assembler-times {vremu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 47 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c
index cb5a1dbc9ffaa3e271f5d3ef307b62926297019a..ee8da2573c706b11de05d1cdaae3220b55f953c6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c
@@ -53,5 +53,5 @@ DEF_OP_VV (shift, 128, int64_t, >>)
 DEF_OP_VV (shift, 256, int64_t, >>)
 DEF_OP_VV (shift, 512, int64_t, >>)
 
-/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
+/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 35 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c
index e626a52c2d88483d56363f52eba89b7407422f61..ebd5575f26727f7d267166a76f068ceeeca4ea56 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c
@@ -53,5 +53,5 @@ DEF_OP_VV (shift, 128, uint64_t, >>)
 DEF_OP_VV (shift, 256, uint64_t, >>)
 DEF_OP_VV (shift, 512, uint64_t, >>)
 
-/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
+/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */