arm64: dts: imx8mp: Configure VPU clocks for overdrive

The defaults for this SoC are configured for overdrive mode, but
the VPU clocks are currently configured for nominal mode.
Increase VPU_G1_CLK_ROOT to 800MHZ from 600MHz,
Increase VPU_G2_CLK_ROOT to 700MHZ from 500MHz, and
Increase VPU_BUS_CLK_ROOT to 800MHz from 600MHz.

This requires adjusting the clock parents. Since there is already
800MHz clock references, move the VPU_BUS and G1 clocks to it.
This frees up the VPU_PLL to be configured at 700MHz to run
the G2 clock at 700MHz.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 43b0d8e1f4b95762ae9e88bb48283fd93a659024..bb24dba7338ea00dd50c5f7e409d72ecb7d790b9 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -2264,8 +2264,8 @@
                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
                        assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;
-                       assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
-                       assigned-clock-rates = <600000000>;
+                       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
+                       assigned-clock-rates = <800000000>;
                        power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;
                };
 
@@ -2274,9 +2274,9 @@
                        reg = <0x38310000 0x10000>;
                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
-                       assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;
-                       assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
-                       assigned-clock-rates = <500000000>;
+                       assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>, <&clk IMX8MP_VPU_PLL_OUT>;
+                       assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
+                       assigned-clock-rates = <700000000>, <700000000>;
                        power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;
                };
 
@@ -2291,9 +2291,9 @@
                                 <&clk IMX8MP_CLK_VPU_G2_ROOT>,
                                 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
                        clock-names = "g1", "g2", "vc8000e";
-                       assigned-clocks = <&clk IMX8MP_VPU_PLL>, <&clk IMX8MP_CLK_VPU_BUS>;
-                       assigned-clock-parents = <0>, <&clk IMX8MP_VPU_PLL_OUT>;
-                       assigned-clock-rates = <600000000>, <600000000>;
+                       assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>;
+                       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
+                       assigned-clock-rates = <800000000>;
                        interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>,
                                        <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>,
                                        <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;