tools/testing/cxl: Fix root port to host bridge assignment

[ Upstream commit a4a0ce242fcd7022349212c4e2f795762e6ff050 ]

Mocked root-ports are meant to be round-robin assigned to host-bridges.

Fixes: 67dcdd4d3b83 ("tools/testing/cxl: Introduce a mocked-up CXL port hierarchy")
Link: https://lore.kernel.org/r/164298431629.3018233.14004377108116384485.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
index cb32f9e27d5d9c02f561f963e375f4c4a209c11b..5a39b3fdcac42116c2836ff3c78ea58351fdf97c 100644 (file)
--- a/tools/testing/cxl/test/cxl.c
+++ b/tools/testing/cxl/test/cxl.c
@@ -488,7 +488,7 @@ static __init int cxl_test_init(void)
 
        for (i = 0; i < ARRAY_SIZE(cxl_root_port); i++) {
                struct platform_device *bridge =
-                       cxl_host_bridge[i / NR_CXL_ROOT_PORTS];
+                       cxl_host_bridge[i % ARRAY_SIZE(cxl_host_bridge)];
                struct platform_device *pdev;
 
                pdev = platform_device_alloc("cxl_root_port", i);