octeontx2-vf: clear stale mailbox IRQ state before request_irq()

otx2vf_register_mbox_intr() currently installs the VF mailbox IRQ
handler before clearing stale mailbox interrupt state. The code then says
that local interrupt bits should be cleared first to avoid spurious
interrupts, but that clear still happens only after request_irq() has
already made the handler reachable.

A running system can reach this during VF mailbox interrupt registration
while stale or latched RVU_VF_INT state is still present. If delivery
happens in the request_irq()-to-clear window,
otx2vf_vfaf_mbox_intr_handler() can run before local quiesce and touch
the same vf->mbox and vf->mbox_wq carrier that probe and teardown later
reuse or destroy.

Move the stale mailbox interrupt clear ahead of request_irq(), but keep
interrupt enabling after the handler is installed. This closes the
pre-clear early-IRQ window without creating a new enable-before-handler
window.

Fixes: 3184fb5ba96e ("octeontx2-vf: Virtual function driver support")
Cc: stable@vger.kernel.org
Signed-off-by: Runyu Xiao <runyu.xiao@seu.edu.cn>
Reviewed-by: Simon Horman <horms@kernel.org>
Reviewed-by: Ratheesh Kannoth <rkannoth@marvell.com>
Link: https://patch.msgid.link/20260611160014.3202224-3-runyu.xiao@seu.edu.cn
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
index f4fdbfba866764477d7c72f4f71da9beb0f61f5c..b022f52c684508d0b5526e5ba21ebf8f8441fd21 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
@@ -251,9 +251,17 @@ static int otx2vf_register_mbox_intr(struct otx2_nic *vf, bool probe_pf)
 {
        struct otx2_hw *hw = &vf->hw;
        struct msg_req *req;
+       u64 mbox_int_mask;
        char *irq_name;
        int err;
 
+       mbox_int_mask = !is_cn20k(vf->pdev) ? BIT_ULL(0) :
+                               BIT_ULL(0) | BIT_ULL(1) |
+                               BIT_ULL(2) | BIT_ULL(3);
+
+       /* Clear stale mailbox interrupt state before installing the handler. */
+       otx2_write64(vf, RVU_VF_INT, mbox_int_mask);
+
        /* Register mailbox interrupt handler */
        irq_name = &hw->irq_name[RVU_VF_INT_VEC_MBOX * NAME_SIZE];
        snprintf(irq_name, NAME_SIZE, "RVUVF%d AFVF Mbox", ((vf->pcifunc &
@@ -274,18 +282,8 @@ static int otx2vf_register_mbox_intr(struct otx2_nic *vf, bool probe_pf)
                return err;
        }
 
-       /* Enable mailbox interrupt for msgs coming from PF.
-        * First clear to avoid spurious interrupts, if any.
-        */
-       if (!is_cn20k(vf->pdev)) {
-               otx2_write64(vf, RVU_VF_INT, BIT_ULL(0));
-               otx2_write64(vf, RVU_VF_INT_ENA_W1S, BIT_ULL(0));
-       } else {
-               otx2_write64(vf, RVU_VF_INT, BIT_ULL(0) | BIT_ULL(1) |
-                            BIT_ULL(2) | BIT_ULL(3));
-               otx2_write64(vf, RVU_VF_INT_ENA_W1S, BIT_ULL(0) |
-                            BIT_ULL(1) | BIT_ULL(2) | BIT_ULL(3));
-       }
+       /* Enable mailbox interrupt for msgs coming from PF. */
+       otx2_write64(vf, RVU_VF_INT_ENA_W1S, mbox_int_mask);
 
        if (!probe_pf)
                return 0;