RISC-V: Add support for Zvfbfwma extension

This implements the Zvfbfwma extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfwma---vector-bf16-widening-mul-add>

1 In spec: "Zvfbfwma requires the Zvfbfmin extension and the Zfbfmin extension."
  1.1 In Embedded    Processor: Zvfbfwma -> Zvfbfmin -> Zve32f
  1.2 In Application Processor: Zvfbfwma -> Zvfbfmin -> V
  1.3 In both scenarios, there are: Zvfbfwma -> Zfbfmin

2 Depending on different usage scenarios, the Zvfbfwma extension may
depend on 'V' or 'Zve32f'. This patch only implements dependencies in
scenario of Embedded Processor. This is consistent with the processing
strategy in Zvfbfmin. In scenario of Application Processor, it is
necessary to explicitly indicate the dependent 'V' extension.

For relevant information in gcc, please refer to:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=38dd4e26e07c6be7cf4d169141ee4f3a03f3a09d>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfwma.
	(riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

	* NEWS: Updated.
	* testsuite/gas/riscv/march-help.l: Ditto.
	* testsuite/gas/riscv/zvfbfwma.d: New test.
	* testsuite/gas/riscv/zvfbfwma.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VFWMACCBF16_VF): Define.
	(MASK_VFWMACCBF16_VF): Ditto.
	(MATCH_VFWMACCBF16_VV): Ditto.
	(MASK_VFWMACCBF16_VV): Ditto.
	(DECLARE_INSN): New declarations for Zvfbfwma.
	* opcode/riscv.h (enum riscv_insn_class): Add
	INSN_CLASS_ZVFBFWMA

opcodes/ChangeLog:

	* riscv-opc.c: Add Zvfbfwma instructions.

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 0131ce85477e407c4bbebb761ae3d4cfd75e1c04..1fe7e5d3df2de243d0eef707d772996335b5acce 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1193,6 +1193,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"v", "zvl128b",     check_implicit_always},
   {"zabha", "a",       check_implicit_always},
   {"zvfbfmin", "zve32f",       check_implicit_always},
+  {"zvfbfwma", "zve32f",       check_implicit_always},
+  {"zvfbfwma", "zfbfmin",      check_implicit_always},
   {"zvfh", "zvfhmin",  check_implicit_always},
   {"zvfh", "zfhmin",   check_implicit_always},
   {"zvfhmin", "zve32f",        check_implicit_always},
@@ -1395,6 +1397,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvbb",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvbc",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvfbfmin",         ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
+  {"zvfbfwma",         ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvfh",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvfhmin",          ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvkb",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
@@ -2651,6 +2654,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvbc");
     case INSN_CLASS_ZVFBFMIN:
       return riscv_subset_supports (rps, "zvfbfmin");
+    case INSN_CLASS_ZVFBFWMA:
+      return riscv_subset_supports (rps, "zvfbfwma");
     case INSN_CLASS_ZVKB:
       return riscv_subset_supports (rps, "zvkb");
     case INSN_CLASS_ZVKG:
@@ -2923,6 +2928,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvbc");
     case INSN_CLASS_ZVFBFMIN:
       return "zvfbfmin";
+    case INSN_CLASS_ZVFBFWMA:
+      return "zvfbfwma";
     case INSN_CLASS_ZVKB:
       return _("zvkb");
     case INSN_CLASS_ZVKG:

diff --git a/gas/NEWS b/gas/NEWS
index a668a52177229481ec96e79b16d69292757a2914..145ce413bff5b34143d1d2ebf27f7153d96ac5ea 100644 (file)
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -25,6 +25,8 @@
 
 * Add support for RISC-V Zvfbfmin extension with version 1.0.
 
+* Add support for RISC-V Zvfbfwma extension with version 1.0.
+
 * The base register operand in D(X,B) and D(L,B) may be explicitly omitted
   in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0)
   D(X,%r0), D(L,0), and D(L,%r0).

diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 38c70e269bf51761dd15240656c8e537e068a53b..dd82752cd30d4b9496b3527a1665c6f35ecfefda 100644 (file)
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -59,6 +59,7 @@ All available -march extensions for RISC-V:
        zvbb                                    1.0
        zvbc                                    1.0
        zvfbfmin                                1.0
+       zvfbfwma                                1.0
        zvfh                                    1.0
        zvfhmin                                 1.0
        zvkb                                    1.0

diff --git a/gas/testsuite/gas/riscv/zvfbfwma.d b/gas/testsuite/gas/riscv/zvfbfwma.d
new file mode 100644 (file)
index 0000000..05da132
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvfbfwma.d
@@ -0,0 +1,12 @@
+#as: -march=rv64iv_zvfbfwma
+#objdump: -d
+
+.*:[   ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[      ]+[0-9a-f]+:[   ]+ee865257[     ]+vfwmaccbf16.vf[       ]+v4,fa2,v8
+[      ]+[0-9a-f]+:[   ]+ec865257[     ]+vfwmaccbf16.vf[       ]+v4,fa2,v8,v0.t
+[      ]+[0-9a-f]+:[   ]+ee861257[     ]+vfwmaccbf16.vv[       ]+v4,v12,v8
+[      ]+[0-9a-f]+:[   ]+ec861257[     ]+vfwmaccbf16.vv[       ]+v4,v12,v8,v0.t

diff --git a/gas/testsuite/gas/riscv/zvfbfwma.s b/gas/testsuite/gas/riscv/zvfbfwma.s
new file mode 100644 (file)
index 0000000..f824af9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvfbfwma.s
@@ -0,0 +1,7 @@
+target:
+       # vfwmaccbf16.vf
+       vfwmaccbf16.vf v4, fa2, v8
+       vfwmaccbf16.vf v4, fa2, v8, v0.t
+       # vfwmaccbf16.vv
+       vfwmaccbf16.vv v4, v12, v8
+       vfwmaccbf16.vv v4, v12, v8, v0.t

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index c5270d017b22bc27815bd4666ac9a0486196b819..e8c08e800c65916546c9926a176ef0b1c65aaa32 100644 (file)
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2375,6 +2375,11 @@
 #define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f
 #define MATCH_VFWCVTBF16_F_F_V 0x48069057
 #define MASK_VFWCVTBF16_F_F_V 0xfc0ff07f
+/* Zvfbfwma intructions.  */
+#define MATCH_VFWMACCBF16_VF 0xec005057
+#define MASK_VFWMACCBF16_VF 0xfc00707f
+#define MATCH_VFWMACCBF16_VV 0xec001057
+#define MASK_VFWMACCBF16_VV 0xfc00707f
 /* Vendor-specific (CORE-V) Xcvmac instructions.  */
 #define MATCH_CV_MAC       0x9000302b
 #define MASK_CV_MAC        0xfe00707f
@@ -3985,6 +3990,9 @@ DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16)
 /* Zvfbfmin instructions.  */
 DECLARE_INSN(VFNCVTBF16_F_F_W, MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W)
 DECLARE_INSN(VFWCVTBF16_F_F_V, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V)
+/* Zvfbfwma instructions.  */
+DECLARE_INSN(VFWMACCBF16_VF, MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF)
+DECLARE_INSN(VFWMACCBF16_VV, MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV)
 /* Zvbb/Zvkb instructions.  */
 DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
 DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)

diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 06415634c7f672905972e46606d464f2e3a3a7f2..33df56d13af7cba56e752761c32039eee76888c3 100644 (file)
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -475,6 +475,7 @@ enum riscv_insn_class
   INSN_CLASS_ZVBB,
   INSN_CLASS_ZVBC,
   INSN_CLASS_ZVFBFMIN,
+  INSN_CLASS_ZVFBFWMA,
   INSN_CLASS_ZVKB,
   INSN_CLASS_ZVKG,
   INSN_CLASS_ZVKNED,

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index eccd3f6fae1130b871098102ef96cf31e433de87..ff08bd595c01d5c5e7bb5bd78d7d514e67cf5866 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2021,6 +2021,10 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vfncvtbf16.f.f.w", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W, match_opcode, 0},
 {"vfwcvtbf16.f.f.v", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V, match_opcode, 0},
 
+/* Zvfbfwma instructions.  */
+{"vfwmaccbf16.vf",  0, INSN_CLASS_ZVFBFWMA, "Vd,S,VtVm",  MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF, match_opcode, 0},
+{"vfwmaccbf16.vv",  0, INSN_CLASS_ZVFBFWMA, "Vd,Vs,VtVm", MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV, match_opcode, 0},
+
 /* Zvbb/Zvkb instructions.  */
 {"vandn.vv",   0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VANDN_VV, MASK_VANDN_VV, match_opcode, 0},
 {"vandn.vx",   0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDN_VX, MASK_VANDN_VX, match_opcode, 0},