Pull Allwinner clk driver updates from Chen-Yu Tsai:
- Add Allwinner A523's missing PPU0 reset (both DT binding and
driver) The binding change is shared with the soc tree.
- Fix Allwinner V3s DE clock mux field width
- Stop passing rate change requests to parent for Allwinner V3s
DE clock
- Force and lock Allwinner V3s DE and TCON clocks to the same
parent, the video PLL
* tag 'sunxi-clk-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: ccu_nm: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_nkmp: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_nk: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_gate: convert from round_rate() to determine_rate()
clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pll
clk: sunxi-ng: v3s: Fix de clock definition
clk: sunxi-ng: sun55i-a523-r-ccu: Add missing PPU0 reset
dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset