drm/amd/pm: Disable SCLK switching on Oland with high pixel clocks (v3)

[ Upstream commit 7009e3af0474aca5f64262b3c72fb6e23b232f9b ]

Port of commit 227545b9a08c ("drm/radeon/dpm: Disable sclk
switching on Oland when two 4K 60Hz monitors are connected")

This is an ad-hoc DPM fix, necessary because we don't have
proper bandwidth calculation for DCE 6.

We define "high pixelclock" for SI as higher than necessary
for 4K 30Hz. For example, 4K 60Hz and 1080p 144Hz fall into
this category.

When two high pixel clock displays are connected to Oland,
additionally disable shader clock switching, which results in
a higher voltage, thereby addressing some visible flickering.

v2:
Add more comments.
v3:
Split into two commits for easier review.

Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
index b3c011542daf706c7ed52eba96cb5cda71e07f5d..7a85c042a6db9ff19d0ea2e93e44428fb6223c75 100644 (file)
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
@@ -3430,12 +3430,14 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
 {
        struct  si_ps *ps = si_get_ps(rps);
        struct amdgpu_clock_and_voltage_limits *max_limits;
+       struct amdgpu_connector *conn;
        bool disable_mclk_switching = false;
        bool disable_sclk_switching = false;
        u32 mclk, sclk;
        u16 vddc, vddci, min_vce_voltage = 0;
        u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
        u32 max_sclk = 0, max_mclk = 0;
+       u32 high_pixelclock_count = 0;
        int i;
 
        if (adev->asic_type == CHIP_HAINAN) {
@@ -3463,6 +3465,35 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
                }
        }
 
+       /* We define "high pixelclock" for SI as higher than necessary for 4K 30Hz.
+        * For example, 4K 60Hz and 1080p 144Hz fall into this category.
+        * Find number of such displays connected.
+        */
+       for (i = 0; i < adev->mode_info.num_crtc; i++) {
+               if (!(adev->pm.dpm.new_active_crtcs & (1 << i)) ||
+                       !adev->mode_info.crtcs[i]->enabled)
+                       continue;
+
+               conn = to_amdgpu_connector(adev->mode_info.crtcs[i]->connector);
+
+               if (conn->pixelclock_for_modeset > 297000)
+                       high_pixelclock_count++;
+       }
+
+       /* These are some ad-hoc fixes to some issues observed with SI GPUs.
+        * They are necessary because we don't have something like dce_calcs
+        * for these GPUs to calculate bandwidth requirements.
+        */
+       if (high_pixelclock_count) {
+               /* On Oland, we observe some flickering when two 4K 60Hz
+                * displays are connected, possibly because voltage is too low.
+                * Raise the voltage by requiring a higher SCLK.
+                * (Voltage cannot be adjusted independently without also SCLK.)
+                */
+               if (high_pixelclock_count > 1 && adev->asic_type == CHIP_OLAND)
+                       disable_sclk_switching = true;
+       }
+
        if (rps->vce_active) {
                rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
                rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;