#include <asm/mpc8xxx_spi.h>
#include <asm/fsl_lbc.h>
#include <asm/fsl_dma.h>
+#include <linux/build_bug.h>
/*
* Local Access Window
u32 bar; /* LBIU local access window base address register */
u32 ar; /* LBIU local access window attribute register */
} law83xx_t;
+static_assert(sizeof(law83xx_t) == 8);
/*
* System configuration registers
#endif
u8 res9[0xB8];
} sysconf83xx_t;
+static_assert(sizeof(sysconf83xx_t) == 0x200);
/*
* Watch Dog Timer (WDT) Registers
u16 swsrr; /* System watchdog service register */
u8 res2[0xF0];
} wdt83xx_t;
+static_assert(sizeof(wdt83xx_t) == 0x100);
/*
* RTC/PIT Module Registers
u32 alr; /* alarm register */
u8 res0[0xE8];
} rtclk83xx_t;
+static_assert(sizeof(rtclk83xx_t) == 0x100);
/*
* Global timer module
u16 psr4; /* Timer4 Prescaler Register */
u8 res[0xC0];
} gtm83xx_t;
+static_assert(sizeof(gtm83xx_t) == 0x100);
/*
* Integrated Programmable Interrupt Controller
u32 smvcr; /* System Management Interrupt Vector Register */
u8 res[0x98];
} ipic83xx_t;
+static_assert(sizeof(ipic83xx_t) == 0x100);
/*
* System Arbiter Registers
u32 aerr; /* Arbiter Event Response Register */
u8 res1[0xDC];
} arbiter83xx_t;
+static_assert(sizeof(arbiter83xx_t) == 0x100);
/*
* Reset Module
u32 rcer; /* Reset Control Enable Register */
u8 res1[0xDC];
} reset83xx_t;
+static_assert(sizeof(reset83xx_t) == 0x100);
/*
* Clock Module
u32 sccr; /* system clock control Register */
u8 res0[0xF4];
} clk83xx_t;
+static_assert(sizeof(clk83xx_t) == 0x100);
/*
* Power Management Control Module
u32 pmccr2; /* PMC Configuration Register 2 */
u8 res0[0xEC];
} pmc83xx_t;
+static_assert(sizeof(pmc83xx_t) == 0x100);
/*
* General purpose I/O module
u32 icr; /* external interrupt control register */
u8 res0[0xE8];
} gpio83xx_t;
+static_assert(sizeof(gpio83xx_t) == 0x100);
/*
* QE Ports Interrupts Registers
u32 qepicr; /* QE Ports Interrupt Control Register */
u8 res1[0xE8];
} qepi83xx_t;
+static_assert(sizeof(qepi83xx_t) == 0x100);
/*
* QE Parallel I/O Ports
u32 ppar1; /* Pin Assignment Register 1 */
u32 ppar2; /* Pin Assignment Register 2 */
} gpio_n_t;
+static_assert(sizeof(gpio_n_t) == 0x18);
typedef struct qegpio83xx {
gpio_n_t ioport[0x7];
u8 res0[0x358];
} qepio83xx_t;
+static_assert(sizeof(qepio83xx_t) == 0x400);
/*
* QE Secondary Bus Access Windows
u32 sdmcar; /* Secondary DDR memory controller attributes */
u8 res2[0x378];
} qesba83xx_t;
+static_assert(sizeof(qesba83xx_t) == 0x400);
/*
* DDR Memory Controller Memory Map for DDR1
u32 csbnds;
u8 res0[4];
} ddr_cs_bnds_t;
+static_assert(sizeof(ddr_cs_bnds_t) == 8);
typedef struct ddr83xx {
ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
u32 debug_reg;
u8 res9[0xFC];
} ddr83xx_t;
+static_assert(sizeof(ddr83xx_t) == 0x1000);
#endif
/*
u8 res1[3];
u8 res2[0xEC];
} duart83xx_t;
+static_assert(sizeof(duart83xx_t) == 0x100);
/*
* DMA/Messaging Unit
u32 res4[0x1E]; /* 0x88-0x99 reserved */
struct fsl_dma dma[4];
} dma83xx_t;
+static_assert(sizeof(dma83xx_t) == 0x300);
/*
* PCI Software Configuration Registers
u32 int_ack;
u8 res[116];
} pciconf83xx_t;
+static_assert(sizeof(pciconf83xx_t) == 0x80);
/*
* PCI Outbound Translation Register
u32 pocmr;
u8 res2[4];
} pot83xx_t;
+static_assert(sizeof(pot83xx_t) == 0x18);
/*
* Sequencer
u32 dtcr;
u8 res2[4];
} ios83xx_t;
+static_assert(sizeof(ios83xx_t) == 0x100);
/*
* PCI Controller Control and Status Registers
u32 piwar0;
u8 res7[132];
} pcictrl83xx_t;
+static_assert(sizeof(pcictrl83xx_t) == 0x100);
/*
* USB
typedef struct usb83xx {
u8 fixme[0x1000];
} usb83xx_t;
+static_assert(sizeof(usb83xx_t) == 0x1000);
/*
* TSEC
typedef struct tsec83xx {
u8 fixme[0x1000];
} tsec83xx_t;
+static_assert(sizeof(tsec83xx_t) == 0x1000);
/*
* Security
typedef struct security83xx {
u8 fixme[0x10000];
} security83xx_t;
+static_assert(sizeof(security83xx_t) == 0x10000);
/*
* PCI Express
struct pex_csb_bridge bridge;
u8 res12[0x160];
} pex83xx_t;
+static_assert(sizeof(pex83xx_t) == 0x1000);
/*
* SATA
typedef struct sata83xx {
u8 fixme[0x1000];
} sata83xx_t;
+static_assert(sizeof(sata83xx_t) == 0x1000);
/*
* eSDHC
typedef struct sdhc83xx {
u8 fixme[0x1000];
} sdhc83xx_t;
+static_assert(sizeof(sdhc83xx_t) == 0x1000);
/*
* SerDes
u32 srdsrstctl;
u8 res1[0xdc];
} serdes83xx_t;
+static_assert(sizeof(serdes83xx_t) == 0x100);
/*
* On Chip ROM
typedef struct tdm83xx {
u8 fixme[0x200];
} tdm83xx_t;
+static_assert(sizeof(tdm83xx_t) == 0x200);
/*
* TDM DMAC
typedef struct tdmdmac83xx {
u8 fixme[0x2000];
} tdmdmac83xx_t;
+static_assert(sizeof(tdmdmac83xx_t) == 0x2000);
#if defined(CONFIG_ARCH_MPC834X)
typedef struct immap {
serdes83xx_t serdes[1]; /* SerDes Registers */
u8 res9[0x1CF00];
} immap_t;
+static_assert(sizeof(immap_t) == 0x100000);
#elif defined(CONFIG_ARCH_MPC837X)
typedef struct immap {
u8 res11[0xCE00];
rom83xx_t rom; /* On Chip ROM */
} immap_t;
+static_assert(sizeof(immap_t) == 0x100000);
#elif defined(CONFIG_ARCH_MPC8360)
typedef struct immap {
u8 res10[0xC0000];
u8 qe[0x100000]; /* QE block */
} immap_t;
+static_assert(sizeof(immap_t) == 0x200000);
#elif defined(CONFIG_ARCH_MPC832X)
typedef struct immap {
u8 res8[0xC0000];
u8 qe[0x100000]; /* QE block */
} immap_t;
+static_assert(sizeof(immap_t) == 0x200000);
#endif
struct ccsr_gpio {