ASoC: tegra: Add AHUB writeable_reg for RX holes

Add writeable_reg callbacks for Tegra210/186 AHUB RX registers so the
flat cache only treats valid RX locations as writable, avoiding holes
in the register map.

Fixes: 16e1bcc2caf4 ("ASoC: tegra: Add Tegra210 based AHUB driver")
Signed-off-by: Sheetal <sheetal@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260123095346.1258556-2-sheetal@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/tegra/tegra210_ahub.c b/sound/soc/tegra/tegra210_ahub.c
index e795907a3963afcffae4b92e7878562fe1aa4a39..fc5892056f832fa95363e29ca8284776a8e25f80 100644 (file)
--- a/sound/soc/tegra/tegra210_ahub.c
+++ b/sound/soc/tegra/tegra210_ahub.c
@@ -2049,6 +2049,61 @@ static const struct snd_soc_component_driver tegra264_ahub_component = {
        .num_dapm_routes        = ARRAY_SIZE(tegra264_ahub_routes),
 };
 
+static bool tegra210_ahub_wr_reg(struct device *dev, unsigned int reg)
+{
+       int part;
+
+       if (reg % TEGRA210_XBAR_RX_STRIDE)
+               return false;
+
+       for (part = 0; part < TEGRA210_XBAR_UPDATE_MAX_REG; part++) {
+               switch (reg & ~(part * TEGRA210_XBAR_PART1_RX)) {
+               case TEGRA210_AXBAR_PART_0_ADMAIF_RX1_0 ... TEGRA210_AXBAR_PART_0_ADMAIF_RX10_0:
+               case TEGRA210_AXBAR_PART_0_I2S1_RX1_0 ... TEGRA210_AXBAR_PART_0_I2S5_RX1_0:
+               case TEGRA210_AXBAR_PART_0_SFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_SFC4_RX1_0:
+               case TEGRA210_AXBAR_PART_0_MIXER1_RX1_0 ... TEGRA210_AXBAR_PART_0_MIXER1_RX10_0:
+               case TEGRA210_AXBAR_PART_0_SPDIF1_RX1_0 ... TEGRA210_AXBAR_PART_0_SPDIF1_RX2_0:
+               case TEGRA210_AXBAR_PART_0_AFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_AFC6_RX1_0:
+               case TEGRA210_AXBAR_PART_0_OPE1_RX1_0 ... TEGRA210_AXBAR_PART_0_OPE2_RX1_0:
+               case TEGRA210_AXBAR_PART_0_SPKPROT1_RX1_0:
+               case TEGRA210_AXBAR_PART_0_MVC1_RX1_0 ... TEGRA210_AXBAR_PART_0_MVC2_RX1_0:
+               case TEGRA210_AXBAR_PART_0_AMX1_RX1_0 ... TEGRA210_AXBAR_PART_0_ADX2_RX1_0:
+                       return true;
+               default:
+                       break;
+               }
+       }
+
+       return false;
+}
+
+static bool tegra186_ahub_wr_reg(struct device *dev, unsigned int reg)
+{
+       int part;
+
+       if (reg % TEGRA210_XBAR_RX_STRIDE)
+               return false;
+
+       for (part = 0; part < TEGRA186_XBAR_UPDATE_MAX_REG; part++) {
+               switch (reg & ~(part * TEGRA210_XBAR_PART1_RX)) {
+               case TEGRA210_AXBAR_PART_0_ADMAIF_RX1_0 ... TEGRA186_AXBAR_PART_0_I2S6_RX1_0:
+               case TEGRA210_AXBAR_PART_0_SFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_SFC4_RX1_0:
+               case TEGRA210_AXBAR_PART_0_MIXER1_RX1_0 ... TEGRA210_AXBAR_PART_0_MIXER1_RX10_0:
+               case TEGRA186_AXBAR_PART_0_DSPK1_RX1_0 ... TEGRA186_AXBAR_PART_0_DSPK2_RX1_0:
+               case TEGRA210_AXBAR_PART_0_AFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_AFC6_RX1_0:
+               case TEGRA210_AXBAR_PART_0_OPE1_RX1_0:
+               case TEGRA186_AXBAR_PART_0_MVC1_RX1_0 ... TEGRA186_AXBAR_PART_0_MVC2_RX1_0:
+               case TEGRA186_AXBAR_PART_0_AMX1_RX1_0 ... TEGRA186_AXBAR_PART_0_AMX3_RX4_0:
+               case TEGRA210_AXBAR_PART_0_ADX1_RX1_0 ... TEGRA186_AXBAR_PART_0_ASRC1_RX7_0:
+                       return true;
+               default:
+                       break;
+               }
+       }
+
+       return false;
+}
+
 static bool tegra264_ahub_wr_reg(struct device *dev, unsigned int reg)
 {
        int part;
@@ -2076,6 +2131,7 @@ static const struct regmap_config tegra210_ahub_regmap_config = {
        .reg_bits               = 32,
        .val_bits               = 32,
        .reg_stride             = 4,
+       .writeable_reg          = tegra210_ahub_wr_reg,
        .max_register           = TEGRA210_MAX_REGISTER_ADDR,
        .cache_type             = REGCACHE_FLAT,
 };
@@ -2084,6 +2140,7 @@ static const struct regmap_config tegra186_ahub_regmap_config = {
        .reg_bits               = 32,
        .val_bits               = 32,
        .reg_stride             = 4,
+       .writeable_reg          = tegra186_ahub_wr_reg,
        .max_register           = TEGRA186_MAX_REGISTER_ADDR,
        .cache_type             = REGCACHE_FLAT,
 };

diff --git a/sound/soc/tegra/tegra210_ahub.h b/sound/soc/tegra/tegra210_ahub.h
index f355b2cfd19b22b76f28bc23439f6e0277a9c6e0..acbe640dd3b572e9caba19fd11b463fe87f5eebc 100644 (file)
--- a/sound/soc/tegra/tegra210_ahub.h
+++ b/sound/soc/tegra/tegra210_ahub.h
@@ -68,6 +68,36 @@
 #define TEGRA210_MAX_REGISTER_ADDR (TEGRA210_XBAR_PART2_RX +           \
        (TEGRA210_XBAR_RX_STRIDE * (TEGRA210_XBAR_AUDIO_RX_COUNT - 1)))
 
+/* AXBAR register offsets */
+#define TEGRA186_AXBAR_PART_0_AMX1_RX1_0       0x120
+#define TEGRA186_AXBAR_PART_0_AMX3_RX4_0       0x14c
+#define TEGRA186_AXBAR_PART_0_ASRC1_RX7_0      0x1a8
+#define TEGRA186_AXBAR_PART_0_DSPK1_RX1_0      0xc0
+#define TEGRA186_AXBAR_PART_0_DSPK2_RX1_0      0xc4
+#define TEGRA186_AXBAR_PART_0_I2S6_RX1_0       0x54
+#define TEGRA186_AXBAR_PART_0_MVC1_RX1_0       0x110
+#define TEGRA186_AXBAR_PART_0_MVC2_RX1_0       0x114
+#define TEGRA210_AXBAR_PART_0_ADMAIF_RX10_0    0x24
+#define TEGRA210_AXBAR_PART_0_ADMAIF_RX1_0     0x0
+#define TEGRA210_AXBAR_PART_0_ADX1_RX1_0       0x160
+#define TEGRA210_AXBAR_PART_0_ADX2_RX1_0       0x164
+#define TEGRA210_AXBAR_PART_0_AFC1_RX1_0       0xd0
+#define TEGRA210_AXBAR_PART_0_AFC6_RX1_0       0xe4
+#define TEGRA210_AXBAR_PART_0_AMX1_RX1_0       0x140
+#define TEGRA210_AXBAR_PART_0_I2S1_RX1_0       0x40
+#define TEGRA210_AXBAR_PART_0_I2S5_RX1_0       0x50
+#define TEGRA210_AXBAR_PART_0_MIXER1_RX10_0    0xa4
+#define TEGRA210_AXBAR_PART_0_MIXER1_RX1_0     0x80
+#define TEGRA210_AXBAR_PART_0_MVC1_RX1_0       0x120
+#define TEGRA210_AXBAR_PART_0_MVC2_RX1_0       0x124
+#define TEGRA210_AXBAR_PART_0_OPE1_RX1_0       0x100
+#define TEGRA210_AXBAR_PART_0_OPE2_RX1_0       0x104
+#define TEGRA210_AXBAR_PART_0_SFC1_RX1_0       0x60
+#define TEGRA210_AXBAR_PART_0_SFC4_RX1_0       0x6c
+#define TEGRA210_AXBAR_PART_0_SPDIF1_RX1_0     0xc0
+#define TEGRA210_AXBAR_PART_0_SPDIF1_RX2_0     0xc4
+#define TEGRA210_AXBAR_PART_0_SPKPROT1_RX1_0   0x110
+
 #define MUX_REG(id) (TEGRA210_XBAR_RX_STRIDE * (id))
 
 #define MUX_VALUE(npart, nbit) (1 + (nbit) + (npart) * 32)