riscv: dts: spacemit: PCIe and PHY-related updates

Define PCIe and PHY-related Device Tree nodes for the SpacemiT K1 SoC.

Enable the combo PHY and the two PCIe-only PHYs on the Banana Pi BPI-F3
board.  The combo PHY is used for USB on this board, and that will be
enabled when USB 3 support is accepted.

The combo PHY must perform a calibration step to determine configuration
values used by the PCIe-only PHYs.  As a result, it must be enabled if
either of the other two PHYs is enabled.

Signed-off-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Tested-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20251218151235.454997-6-elder@riscstar.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>

diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 71f48454ba47c8a9664af5adf2a80f9c577d4db6..3f10efd925dc8a22493c82bd0cd2cf69a4cd6006 100644 (file)
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -61,6 +61,12 @@
        };
 };
 
+&combo_phy {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie0_3_cfg>;
+       status = "okay";
+};
+
 &emmc {
        bus-width = <8>;
        mmc-hs400-1_8v;
@@ -272,6 +278,36 @@
        };
 };
 
+&pcie1_phy {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie1_3_cfg>;
+       status = "okay";
+};
+
+&pcie1_port {
+       phys = <&pcie1_phy>;
+};
+
+&pcie1 {
+       vpcie3v3-supply = <&pcie_vcc_3v3>;
+       status = "okay";
+};
+
+&pcie2_phy {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie2_4_cfg>;
+       status = "okay";
+};
+
+&pcie2_port {
+       phys = <&pcie2_phy>;
+};
+
+&pcie2 {
+       vpcie3v3-supply = <&pcie_vcc_3v3>;
+       status = "okay";
+};
+
 &uart0 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart0_2_cfg>;

diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
index e922e05ff856df78c90978b0bb312e5d20ef121a..b13dcb10f4d66022d27307de73a6ea3287e97441 100644 (file)
--- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
@@ -530,6 +530,39 @@
                };
        };
 
+       pcie0_3_cfg: pcie0-3-cfg {
+               pcie0-3-pins {
+                       pinmux = <K1_PADCONF(54, 3)>,   /* PERST# */
+                                <K1_PADCONF(55, 3)>,   /* WAKE# */
+                                <K1_PADCONF(53, 3)>;   /* CLKREQ# */
+
+                       bias-pull-up = <0>;
+                       drive-strength = <21>;
+               };
+       };
+
+       pcie1_3_cfg: pcie1-3-cfg {
+               pcie1-3-pins {
+                       pinmux = <K1_PADCONF(59, 4)>,   /* PERST# */
+                                <K1_PADCONF(60, 4)>,   /* WAKE# */
+                                <K1_PADCONF(61, 4)>;   /* CLKREQ# */
+
+                       bias-pull-up = <0>;
+                       drive-strength = <21>;
+               };
+       };
+
+       pcie2_4_cfg: pcie2-4-cfg {
+               pcie2-4-pins {
+                       pinmux = <K1_PADCONF(62, 4)>,   /* PERST# */
+                                <K1_PADCONF(112, 3)>,  /* WAKE# */
+                                <K1_PADCONF(117, 4)>;  /* CLKREQ# */
+
+                       bias-pull-up = <0>;
+                       drive-strength = <21>;
+               };
+       };
+
        pwm14_1_cfg: pwm14-1-cfg {
                pwm14-1-pins {
                        pinmux = <K1_PADCONF(44, 4)>;

diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index 7818ca4979b6a7755722919a5958512aa11950ab..86d1db14e2ee498613542acc3e60789d54762017 100644 (file)
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/clock/spacemit,k1-syscon.h>
+#include <dt-bindings/phy/phy.h>
 
 /dts-v1/;
 / {
@@ -423,6 +424,52 @@
                        status = "disabled";
                };
 
+               combo_phy: phy@c0b10000 {
+                       compatible = "spacemit,k1-combo-phy";
+                       reg = <0x0 0xc0b10000 0x0 0x1000>;
+                       clocks = <&vctcxo_24m>,
+                                <&syscon_apmu CLK_PCIE0_DBI>,
+                                <&syscon_apmu CLK_PCIE0_MASTER>,
+                                <&syscon_apmu CLK_PCIE0_SLAVE>;
+                       clock-names = "refclk",
+                                     "dbi",
+                                     "mstr",
+                                     "slv";
+                       resets = <&syscon_apmu RESET_PCIE0_GLOBAL>,
+                                <&syscon_apmu RESET_PCIE0_DBI>,
+                                <&syscon_apmu RESET_PCIE0_MASTER>,
+                                <&syscon_apmu RESET_PCIE0_SLAVE>;
+                       reset-names = "phy",
+                                     "dbi",
+                                     "mstr",
+                                     "slv";
+                       #phy-cells = <1>;
+                       spacemit,apmu = <&syscon_apmu>;
+                       status = "disabled";
+               };
+
+               pcie1_phy: phy@c0c10000 {
+                       compatible = "spacemit,k1-pcie-phy";
+                       reg = <0x0 0xc0c10000 0x0 0x1000>;
+                       clocks = <&vctcxo_24m>;
+                       clock-names = "refclk";
+                       resets = <&syscon_apmu RESET_PCIE1_GLOBAL>;
+                       reset-names = "phy";
+                       #phy-cells = <0>;
+                       status = "disabled";
+               };
+
+               pcie2_phy: phy@c0d10000 {
+                       compatible = "spacemit,k1-pcie-phy";
+                       reg = <0x0 0xc0d10000 0x0 0x1000>;
+                       clocks = <&vctcxo_24m>;
+                       clock-names = "refclk";
+                       resets = <&syscon_apmu RESET_PCIE2_GLOBAL>;
+                       reset-names = "phy";
+                       #phy-cells = <0>;
+                       status = "disabled";
+               };
+
                syscon_apbc: system-controller@d4015000 {
                        compatible = "spacemit,k1-syscon-apbc";
                        reg = <0x0 0xd4015000 0x0 0x1000>;
@@ -969,6 +1016,135 @@
                        #size-cells = <2>;
                        dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
                                     <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>;
+                       pcie0: pcie@ca000000 {
+                               device_type = "pci";
+                               compatible = "spacemit,k1-pcie";
+                               reg = <0x0 0xca000000 0x0 0x00001000>,
+                                     <0x0 0xca300000 0x0 0x0001ff24>,
+                                     <0x0 0x8f000000 0x0 0x00002000>,
+                                     <0x0 0xc0b20000 0x0 0x00001000>;
+                               reg-names = "dbi",
+                                           "atu",
+                                           "config",
+                                           "link";
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>,
+                                        <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x0f000000>;
+                               interrupts = <141>;
+                               interrupt-names = "msi";
+                               clocks = <&syscon_apmu CLK_PCIE0_DBI>,
+                                        <&syscon_apmu CLK_PCIE0_MASTER>,
+                                        <&syscon_apmu CLK_PCIE0_SLAVE>;
+                               clock-names = "dbi",
+                                             "mstr",
+                                             "slv";
+                               resets = <&syscon_apmu RESET_PCIE0_DBI>,
+                                        <&syscon_apmu RESET_PCIE0_MASTER>,
+                                        <&syscon_apmu RESET_PCIE0_SLAVE>;
+                               reset-names = "dbi",
+                                             "mstr",
+                                             "slv";
+                               spacemit,apmu = <&syscon_apmu 0x03cc>;
+                               status = "disabled";
+
+                               pcie0_port: pcie@0 {
+                                       device_type = "pci";
+                                       compatible = "pciclass,0604";
+                                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                                       bus-range = <0x01 0xff>;
+                                       #address-cells = <3>;
+                                       #size-cells = <2>;
+                                       ranges;
+                               };
+                       };
+
+                       pcie1: pcie@ca400000 {
+                               device_type = "pci";
+                               compatible = "spacemit,k1-pcie";
+                               reg = <0x0 0xca400000 0x0 0x00001000>,
+                                     <0x0 0xca700000 0x0 0x0001ff24>,
+                                     <0x0 0x9f000000 0x0 0x00002000>,
+                                     <0x0 0xc0c20000 0x0 0x00001000>;
+                               reg-names = "dbi",
+                                           "atu",
+                                           "config",
+                                           "link";
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>,
+                                        <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x0f000000>;
+                               interrupts = <142>;
+                               interrupt-names = "msi";
+                               clocks = <&syscon_apmu CLK_PCIE1_DBI>,
+                                        <&syscon_apmu CLK_PCIE1_MASTER>,
+                                        <&syscon_apmu CLK_PCIE1_SLAVE>;
+                               clock-names = "dbi",
+                                             "mstr",
+                                             "slv";
+                               resets = <&syscon_apmu RESET_PCIE1_DBI>,
+                                        <&syscon_apmu RESET_PCIE1_MASTER>,
+                                        <&syscon_apmu RESET_PCIE1_SLAVE>;
+                               reset-names = "dbi",
+                                             "mstr",
+                                             "slv";
+                               spacemit,apmu = <&syscon_apmu 0x3d4>;
+                               status = "disabled";
+
+                               pcie1_port: pcie@0 {
+                                       device_type = "pci";
+                                       compatible = "pciclass,0604";
+                                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                                       bus-range = <0x01 0xff>;
+                                       #address-cells = <3>;
+                                       #size-cells = <2>;
+                                       ranges;
+                               };
+                       };
+
+                       pcie2: pcie@ca800000 {
+                               device_type = "pci";
+                               compatible = "spacemit,k1-pcie";
+                               reg = <0x0 0xca800000 0x0 0x00001000>,
+                                     <0x0 0xcab00000 0x0 0x0001ff24>,
+                                     <0x0 0xb7000000 0x0 0x00002000>,
+                                     <0x0 0xc0d20000 0x0 0x00001000>;
+                               reg-names = "dbi",
+                                           "atu",
+                                           "config",
+                                           "link";
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>,
+                                        <0x42000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000>,
+                                        <0x02000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x07000000>;
+                               interrupts = <143>;
+                               interrupt-names = "msi";
+                               clocks = <&syscon_apmu CLK_PCIE2_DBI>,
+                                        <&syscon_apmu CLK_PCIE2_MASTER>,
+                                        <&syscon_apmu CLK_PCIE2_SLAVE>;
+                               clock-names = "dbi",
+                                             "mstr",
+                                             "slv";
+                               resets = <&syscon_apmu RESET_PCIE2_DBI>,
+                                        <&syscon_apmu RESET_PCIE2_MASTER>,
+                                        <&syscon_apmu RESET_PCIE2_SLAVE>;
+                               reset-names = "dbi",
+                                             "mstr",
+                                             "slv";
+                               spacemit,apmu = <&syscon_apmu 0x3dc>;
+                               status = "disabled";
+
+                               pcie2_port: pcie@0 {
+                                       device_type = "pci";
+                                       compatible = "pciclass,0604";
+                                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                                       bus-range = <0x01 0xff>;
+                                       #address-cells = <3>;
+                                       #size-cells = <2>;
+                                       ranges;
+                               };
+                       };
                };
 
                storage-bus {