]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/amdkfd: refactor rlc/gfx spm
authorJames Zhu <James.Zhu@amd.com>
Fri, 11 Oct 2024 17:40:42 +0000 (13:40 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 8 Dec 2025 18:56:30 +0000 (13:56 -0500)
for adding multiple xcc support.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Bing Ma <Bing.Ma@amd.com>
Reviewed-by: Gang Ba <gaba@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

index 2ce310b319421f7d26d4d9b1f53b718c9d82c0a8..3e2d2e333907daa6c0e1943e962ef1884b11a7c9 100644 (file)
@@ -257,7 +257,8 @@ struct amdgpu_rlc_funcs {
        void (*stop)(struct amdgpu_device *adev);
        void (*reset)(struct amdgpu_device *adev);
        void (*start)(struct amdgpu_device *adev);
-       void (*update_spm_vmid)(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid);
+       void (*update_spm_vmid)(struct amdgpu_device *adev, int xcc_id,
+                       struct amdgpu_ring *ring, unsigned vmid);
        bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);
 };
 
index a67285118c37ba68a97e395fcf389a99d9207128..3b002e37b55beffc1bd9f268edf912655e27554b 100644 (file)
@@ -834,7 +834,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
                amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
 
        if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid)
-               adev->gfx.rlc.funcs->update_spm_vmid(adev, ring, job->vmid);
+               adev->gfx.rlc.funcs->update_spm_vmid(adev, ring->xcc_id, ring, job->vmid);
 
        if (ring->funcs->emit_gds_switch &&
            gds_switch_needed) {
index d75b9940f24874aaee983a37c1186e998f2e3b10..aaed24f7e71682d9407bd1252c52479ea6b660df 100644 (file)
@@ -8318,7 +8318,8 @@ static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
        }
 }
 
-static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)
+static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
+               struct amdgpu_ring *ring, unsigned int vmid)
 {
        amdgpu_gfx_off_ctrl(adev, false);
 
index 831b4268e099bd8a38773376b6d59f0e175d0359..f4d4dd5dd07b5987d5bd07698a01b365fe50ecbd 100644 (file)
@@ -918,7 +918,7 @@ static int gfx_v11_0_rlc_init(struct amdgpu_device *adev)
 
        /* init spm vmid with 0xf */
        if (adev->gfx.rlc.funcs->update_spm_vmid)
-               adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
+               adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf);
 
        return 0;
 }
@@ -5569,7 +5569,8 @@ static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
        return 0;
 }
 
-static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid)
+static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
+               struct amdgpu_ring *ring, unsigned vmid)
 {
        u32 reg, pre_data, data;
 
index 9a18df09503731b2af8c32e3b0baf842dd4dfabf..f9cae666669738f24a21845bda2dd504304a8008 100644 (file)
@@ -762,7 +762,7 @@ static int gfx_v12_0_rlc_init(struct amdgpu_device *adev)
 
        /* init spm vmid with 0xf */
        if (adev->gfx.rlc.funcs->update_spm_vmid)
-               adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
+               adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf);
 
        return 0;
 }
@@ -3957,6 +3957,7 @@ static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,
 }
 
 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev,
+                                     int xcc_id,
                                      struct amdgpu_ring *ring,
                                      unsigned vmid)
 {
index 2b7aba22ecc19031c4340fffd46c570d9577e1e4..66a4e4998106f7006e490b26dd178aa751663237 100644 (file)
@@ -3245,7 +3245,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
 
        /* init spm vmid with 0xf */
        if (adev->gfx.rlc.funcs->update_spm_vmid)
-               adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
+               adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf);
 
        return 0;
 }
@@ -3471,7 +3471,8 @@ static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
        return 0;
 }
 
-static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid)
+static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
+               struct amdgpu_ring *ring, unsigned vmid)
 {
        u32 data;
 
index 1c87375e1dd5874754ec817486601a538a95923a..5d6e8e0601cb75630e37ae844a226e6a8a9c6610 100644 (file)
@@ -1274,7 +1274,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
 
        /* init spm vmid with 0xf */
        if (adev->gfx.rlc.funcs->update_spm_vmid)
-               adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
+               adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf);
 
        return 0;
 }
@@ -5541,7 +5541,8 @@ static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
        }
 }
 
-static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid)
+static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
+               struct amdgpu_ring *ring, unsigned vmid)
 {
        u32 data;
 
index 0148d7ff34d99a9c8f8d507a19fdb1e4a9f139c3..e6187be27385ab3e736654d423b6b4fd799b51d7 100644 (file)
@@ -5171,7 +5171,8 @@ static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev,
                WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
 }
 
-static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)
+static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
+               struct amdgpu_ring *ring, unsigned int vmid)
 {
        amdgpu_gfx_off_ctrl(adev, false);
 
index cbb74ffc479257cba532dad925e71aa09d018aaa..89253df5ffc85add31f48f7301af71404a56d1dd 100644 (file)
@@ -1455,7 +1455,7 @@ static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev)
 {
        /* init spm vmid with 0xf */
        if (adev->gfx.rlc.funcs->update_spm_vmid)
-               adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
+               adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf);
 
        return 0;
 }
@@ -1666,12 +1666,12 @@ static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev)
        return 0;
 }
 
-static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring,
-                                      unsigned vmid)
+static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev,
+                                             int inst, struct amdgpu_ring *ring, unsigned int vmid)
 {
        u32 reg, pre_data, data;
 
-       reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL);
+       reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL);
        if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev))
                pre_data = RREG32_NO_KIQ(reg);
        else
@@ -1682,9 +1682,9 @@ static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu
 
        if (pre_data != data) {
                if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) {
-                       WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);
+                       WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data);
                } else
-                       WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);
+                       WREG32_SOC15(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data);
        }
 }