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arm: [MVE intrinsics] factorize vrev16q vrev32q vrev64q
authorChristophe Lyon <christophe.lyon@arm.com>
Tue, 21 Feb 2023 08:46:02 +0000 (08:46 +0000)
committerChristophe Lyon <christophe.lyon@arm.com>
Thu, 11 May 2023 08:25:09 +0000 (10:25 +0200)
Factorize vrev16q vrev32q vrev64q so that they use generic builtin
names.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (MVE_V8HF, MVE_V16QI)
(MVE_FP_VREV64Q_ONLY, MVE_FP_M_VREV64Q_ONLY, MVE_FP_VREV32Q_ONLY)
(MVE_FP_M_VREV32Q_ONLY): New iterators.
(mve_insn): Add vrev16q, vrev32q, vrev64q.
* config/arm/mve.md (mve_vrev64q_f<mode>): Rename into ...
(@mve_<mve_insn>q_f<mode>): ... this
(mve_vrev32q_fv8hf): Rename into @mve_<mve_insn>q_f<mode>.
(mve_vrev64q_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vrev32q_<supf><mode>): Rename into
@mve_<mve_insn>q_<supf><mode>.
(mve_vrev16q_<supf>v16qi): Rename into
@mve_<mve_insn>q_<supf><mode>.
(mve_vrev64q_m_<supf><mode>): Rename into
@mve_<mve_insn>q_m_<supf><mode>.
(mve_vrev32q_m_fv8hf): Rename into @mve_<mve_insn>q_m_f<mode>.
(mve_vrev32q_m_<supf><mode>): Rename into
@mve_<mve_insn>q_m_<supf><mode>.
(mve_vrev64q_m_f<mode>): Rename into @mve_<mve_insn>q_m_f<mode>.
(mve_vrev16q_m_<supf>v16qi): Rename into
@mve_<mve_insn>q_m_<supf><mode>.

gcc/config/arm/iterators.md patch | blob | blame | history
gcc/config/arm/mve.md patch | blob | blame | history

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index ef9fae0412bc5beae60e2cb6c2ecf399778213d9..878210471c8b20c9d94bcc6a6e896c5b983cbeb1 100644 (file)
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -1,3 +1,4 @@
+
 ;; Code and mode itertator and attribute definitions for the ARM backend
 ;; Copyright (C) 2010-2023 Free Software Foundation, Inc.
 ;; Contributed by ARM Ltd.
@@ -274,6 +275,8 @@
 (define_mode_iterator MVE_6 [V8HI V4SI])
 (define_mode_iterator MVE_7 [V16BI V8BI V4BI V2QI])
 (define_mode_iterator MVE_7_HI [HI V16BI V8BI V4BI V2QI])
+(define_mode_iterator MVE_V8HF [V8HF])
+(define_mode_iterator MVE_V16QI [V16QI])
 
 ;;----------------------------------------------------------------------------
 ;; Code iterators
@@ -372,6 +375,22 @@
                     VRNDXQ_M_F
                     ])
 
+(define_int_iterator MVE_FP_VREV64Q_ONLY [
+                    VREV64Q_F
+                    ])
+
+(define_int_iterator MVE_FP_M_VREV64Q_ONLY [
+                    VREV64Q_M_F
+                    ])
+
+(define_int_iterator MVE_FP_VREV32Q_ONLY [
+                    VREV32Q_F
+                    ])
+
+(define_int_iterator MVE_FP_M_VREV32Q_ONLY [
+                    VREV32Q_M_F
+                    ])
+
 ;; MVE integer binary operations.
 (define_code_iterator MVE_INT_BINARY_RTX [plus minus mult])
 
@@ -862,6 +881,12 @@
                 (VQSUBQ_M_S "vqsub") (VQSUBQ_M_U "vqsub")
                 (VQSUBQ_N_S "vqsub") (VQSUBQ_N_U "vqsub")
                 (VQSUBQ_S "vqsub") (VQSUBQ_U "vqsub")
+                (VREV16Q_M_S "vrev16") (VREV16Q_M_U "vrev16")
+                (VREV16Q_S "vrev16") (VREV16Q_U "vrev16")
+                (VREV32Q_M_S "vrev32") (VREV32Q_M_U "vrev32") (VREV32Q_M_F "vrev32")
+                (VREV32Q_S "vrev32") (VREV32Q_U "vrev32") (VREV32Q_F "vrev32")
+                (VREV64Q_M_S "vrev64") (VREV64Q_M_U "vrev64") (VREV64Q_M_F "vrev64")
+                (VREV64Q_S "vrev64") (VREV64Q_U "vrev64") (VREV64Q_F "vrev64")
                 (VRHADDQ_M_S "vrhadd") (VRHADDQ_M_U "vrhadd")
                 (VRHADDQ_S "vrhadd") (VRHADDQ_U "vrhadd")
                 (VRMULHQ_M_S "vrmulh") (VRMULHQ_M_U "vrmulh")
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 191d1268ad635a3c4752aa447150c3db288406f0..4dfcd6c42808c5e140fbf46a647018f9fd5820a4 100644 (file)
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -151,14 +151,14 @@
 ;;
 ;; [vrev64q_f])
 ;;
-(define_insn "mve_vrev64q_f<mode>"
+(define_insn "@mve_<mve_insn>q_f<mode>"
   [
    (set (match_operand:MVE_0 0 "s_register_operand" "=&w")
        (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
-        VREV64Q_F))
+        MVE_FP_VREV64Q_ONLY))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vrev64.%#<V_sz_elem> %q0, %q1"
+  "<mve_insn>.%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -193,14 +193,14 @@
 ;;
 ;; [vrev32q_f])
 ;;
-(define_insn "mve_vrev32q_fv8hf"
+(define_insn "@mve_<mve_insn>q_f<mode>"
   [
-   (set (match_operand:V8HF 0 "s_register_operand" "=w")
-       (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "w")]
-        VREV32Q_F))
+   (set (match_operand:MVE_V8HF 0 "s_register_operand" "=w")
+       (unspec:MVE_V8HF [(match_operand:MVE_V8HF 1 "s_register_operand" "w")]
+        MVE_FP_VREV32Q_ONLY))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vrev32.16 %q0, %q1"
+  "<mve_insn>.<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 ;;
@@ -248,14 +248,14 @@
 ;;
 ;; [vrev64q_u, vrev64q_s])
 ;;
-(define_insn "mve_vrev64q_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_<supf><mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=&w")
        (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
         VREV64Q))
   ]
   "TARGET_HAVE_MVE"
-  "vrev64.%#<V_sz_elem> %q0, %q1"
+  "<mve_insn>.%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -374,14 +374,14 @@
 ;;
 ;; [vrev32q_u, vrev32q_s])
 ;;
-(define_insn "mve_vrev32q_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_<supf><mode>"
   [
    (set (match_operand:MVE_3 0 "s_register_operand" "=w")
        (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "w")]
         VREV32Q))
   ]
   "TARGET_HAVE_MVE"
-  "vrev32.%#<V_sz_elem>\t%q0, %q1"
+  "<mve_insn>.%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -486,14 +486,14 @@
 ;;
 ;; [vrev16q_u, vrev16q_s])
 ;;
-(define_insn "mve_vrev16q_<supf>v16qi"
+(define_insn "@mve_<mve_insn>q_<supf><mode>"
   [
-   (set (match_operand:V16QI 0 "s_register_operand" "=w")
-       (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "w")]
+   (set (match_operand:MVE_V16QI 0 "s_register_operand" "=w")
+       (unspec:MVE_V16QI [(match_operand:MVE_V16QI 1 "s_register_operand" "w")]
         VREV16Q))
   ]
   "TARGET_HAVE_MVE"
-  "vrev16.8 %q0, %q1"
+  "<mve_insn>.<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2364,7 +2364,7 @@
 ;;
 ;; [vrev64q_m_u, vrev64q_m_s])
 ;;
-(define_insn "mve_vrev64q_m_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_<supf><mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=&w")
        (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
@@ -2373,7 +2373,7 @@
         VREV64Q_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vrev64t.%#<V_sz_elem>\t%q0, %q2"
+  "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -3008,23 +3008,23 @@
 ;;
 ;; [vrev32q_m_f])
 ;;
-(define_insn "mve_vrev32q_m_fv8hf"
+(define_insn "@mve_<mve_insn>q_m_f<mode>"
   [
-   (set (match_operand:V8HF 0 "s_register_operand" "=w")
-       (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
-                      (match_operand:V8HF 2 "s_register_operand" "w")
-                      (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-        VREV32Q_M_F))
+   (set (match_operand:MVE_V8HF 0 "s_register_operand" "=w")
+       (unspec:MVE_V8HF [(match_operand:MVE_V8HF 1 "s_register_operand" "0")
+                         (match_operand:MVE_V8HF 2 "s_register_operand" "w")
+                         (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
+        MVE_FP_M_VREV32Q_ONLY))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vrev32t.16 %q0, %q2"
+  "vpst\;<mve_insn>t.<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
 ;;
 ;; [vrev32q_m_s, vrev32q_m_u])
 ;;
-(define_insn "mve_vrev32q_m_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_<supf><mode>"
   [
    (set (match_operand:MVE_3 0 "s_register_operand" "=w")
        (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "0")
@@ -3033,23 +3033,23 @@
         VREV32Q_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vrev32t.%#<V_sz_elem> %q0, %q2"
+  "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
 ;;
 ;; [vrev64q_m_f])
 ;;
-(define_insn "mve_vrev64q_m_f<mode>"
+(define_insn "@mve_<mve_insn>q_m_f<mode>"
   [
    (set (match_operand:MVE_0 0 "s_register_operand" "=&w")
        (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
                       (match_operand:MVE_0 2 "s_register_operand" "w")
                       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-        VREV64Q_M_F))
+        MVE_FP_M_VREV64Q_ONLY))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vrev64t.%#<V_sz_elem> %q0, %q2"
+  "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -3201,16 +3201,16 @@
 ;;
 ;; [vrev16q_m_u, vrev16q_m_s])
 ;;
-(define_insn "mve_vrev16q_m_<supf>v16qi"
+(define_insn "@mve_<mve_insn>q_m_<supf><mode>"
   [
-   (set (match_operand:V16QI 0 "s_register_operand" "=w")
-       (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "0")
-                      (match_operand:V16QI 2 "s_register_operand" "w")
-                      (match_operand:V16BI 3 "vpr_register_operand" "Up")]
+   (set (match_operand:MVE_V16QI 0 "s_register_operand" "=w")
+       (unspec:MVE_V16QI [(match_operand:MVE_V16QI 1 "s_register_operand" "0")
+                          (match_operand:MVE_V16QI 2 "s_register_operand" "w")
+                          (match_operand:V16BI 3 "vpr_register_operand" "Up")]
         VREV16Q_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vrev16t.8 %q0, %q2"
+  "vpst\;<mve_insn>t.<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
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