net: ravb: Configure CXR31 and CXR35 on rzg2l

As in Linux with d78c0ced60 ("net: ravb: Make write access to CXR35 first
before accessing other EMAC register"), configure CXR31 and CXR35 correctly
on rzg2. MII mode does not work correctly unless those registers are
properly configured.

Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index 68528864ac6838d00819c52af73100d9d486655d..04ee0c0995a5bb37e723f4f0db6af51395c41cf9 100644 (file)
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -42,6 +42,8 @@
 #define RAVB_REG_RFLR          0x508
 #define RAVB_REG_ECSIPR                0x518
 #define RAVB_REG_PIR           0x520
+#define RAVB_REG_CXR31         0x530 /* RZ/G2L only */
+#define RAVB_REG_CXR35         0x540 /* RZ/G2L only */
 #define RAVB_REG_GECMR         0x5b0
 #define RAVB_REG_MAHR          0x5c0
 #define RAVB_REG_MALR          0x5c8
@@ -51,6 +53,12 @@
 #define CCC_OPC_OPERATION      BIT(1)
 #define CCC_BOC                        BIT(20)
 
+#define CXR31_SEL_LINK0         BIT(0)
+#define CXR31_SEL_LINK1         BIT(3)
+
+#define CXR35_SEL_XMII_RGMII    0
+#define CXR35_SEL_XMII_MII      2
+
 #define CSR_OPS                        0x0000000F
 #define CSR_OPS_CONFIG         BIT(1)
 
@@ -399,6 +407,20 @@ static void ravb_mac_init_rcar(struct udevice *dev)
 static void ravb_mac_init_rzg2l(struct udevice *dev)
 {
        struct ravb_priv *eth = dev_get_priv(dev);
+       struct eth_pdata *pdata = dev_get_plat(dev);
+
+       if (pdata->phy_interface == PHY_INTERFACE_MODE_MII) {
+               writel((1000 << 16) | CXR35_SEL_XMII_MII,
+                      eth->iobase + RAVB_REG_CXR35);
+               clrsetbits_32(eth->iobase + RAVB_REG_CXR31,
+                             CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0);
+       } else {
+               writel((1000 << 16) | CXR35_SEL_XMII_RGMII,
+                      eth->iobase + RAVB_REG_CXR35);
+               clrsetbits_32(eth->iobase + RAVB_REG_CXR31,
+                             CXR31_SEL_LINK0 | CXR31_SEL_LINK1,
+                             CXR31_SEL_LINK0);
+       }
 
        setbits_32(eth->iobase + RAVB_REG_ECMR,
                   ECMR_PRM | ECMR_RXF | ECMR_TXF | ECMR_RCPT |