PCI: imx6: Configure REF_USE_PAD before PHY reset for i.MX95

According to the i.MX95 PCIe PHY Databook, the ref_use_pad signal in the
Common Block Signals section selects the reference clock source connected
to the PHY pads. Per the specification, any change to this input must be
followed by a PHY reset assertion to take effect.

Move the REF_USE_PAD configuration before the PHY reset toggle to comply
with the required initialization sequence.

Fixes: 47f54a902dcd ("PCI: imx6: Toggle the core reset for i.MX95 PCIe")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
[mani: renamed the callback and helper to match the usecase]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20260518072715.3166514-2-hongxing.zhu@nxp.com

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 773ab65b2aface07e4d0391e4e0dd12fd60f8910..b32748816ac8674c6e919a605e78c785e9979b5b 100644 (file)
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -138,6 +138,7 @@ struct imx_pcie_drvdata {
        const u32 mode_off[IMX_PCIE_MAX_INSTANCES];
        const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
        const struct pci_epc_features *epc_features;
+       int (*select_ref_clk_src)(struct imx_pcie *pcie);
        int (*init_phy)(struct imx_pcie *pcie);
        int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable);
        int (*core_reset)(struct imx_pcie *pcie, bool assert);
@@ -249,6 +250,24 @@ static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
        return imx_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
 }
 
+static int imx95_pcie_select_ref_clk_src(struct imx_pcie *imx_pcie)
+{
+       bool ext = imx_pcie->enable_ext_refclk;
+
+       /*
+        * Regarding the Signal Descriptions of i.MX95 PCIe PHY, ref_use_pad is
+        * used to select reference clock connected to a pair of pads.
+        *
+        * Any change in this input must be followed by phy_reset assertion.
+        */
+
+       regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_GEN_CTRL,
+                          IMX95_PCIE_REF_USE_PAD,
+                          ext ? IMX95_PCIE_REF_USE_PAD : 0);
+
+       return 0;
+}
+
 static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
 {
        bool ext = imx_pcie->enable_ext_refclk;
@@ -271,9 +290,6 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
                        IMX95_PCIE_PHY_CR_PARA_SEL,
                        IMX95_PCIE_PHY_CR_PARA_SEL);
 
-       regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_GEN_CTRL,
-                          IMX95_PCIE_REF_USE_PAD,
-                          ext ? IMX95_PCIE_REF_USE_PAD : 0);
        regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
                           IMX95_PCIE_REF_CLKEN,
                           ext ? 0 : IMX95_PCIE_REF_CLKEN);
@@ -1351,6 +1367,9 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
                pp->bridge->disable_device = imx_pcie_disable_device;
        }
 
+       if (imx_pcie->drvdata->select_ref_clk_src)
+               imx_pcie->drvdata->select_ref_clk_src(imx_pcie);
+
        imx_pcie_assert_core_reset(imx_pcie);
 
        if (imx_pcie->drvdata->init_phy)
@@ -2051,6 +2070,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
                .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
                .core_reset = imx95_pcie_core_reset,
                .init_phy = imx95_pcie_init_phy,
+               .select_ref_clk_src = imx95_pcie_select_ref_clk_src,
                .wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
                .enable_ref_clk = imx95_pcie_enable_ref_clk,
                .clr_clkreq_override = imx95_pcie_clr_clkreq_override,
@@ -2106,6 +2126,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
                .ltssm_mask = IMX95_PCIE_LTSSM_EN,
                .mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
                .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
+               .select_ref_clk_src = imx95_pcie_select_ref_clk_src,
                .init_phy = imx95_pcie_init_phy,
                .core_reset = imx95_pcie_core_reset,
                .wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,