static Bool guest_rip_next_mustcheck;
-/*------------------------------------------------------------*/
-/*--- For placating icc's typechecker when -Wall applies. ---*/
-/*------------------------------------------------------------*/
-
-static inline UChar and8 ( UChar x, UChar y ) {
- UInt r = x & y;
- return (UChar)r;
-}
-static inline UChar or8 ( UChar x, UChar y ) {
- UInt r = x | y;
- return (UChar)r;
-}
-static inline UChar shr8U ( UChar x, Int n ) {
- UInt r = ((UInt)x) >> n;
- return (UChar)r;
-}
-
-
/*------------------------------------------------------------*/
/*--- Helpers for constructing IR. ---*/
/*------------------------------------------------------------*/
/*IN*/ Bool (*resteerOkFn) ( Addr64 ),
/*IN*/ ULong delta,
/*IN*/ VexSubArch subarch,
- /*OUT*/ UInt* size,
+ /*OUT*/ Long* size,
/*OUT*/ Addr64* whereNext );
Bool host_bigendian,
VexSubArch subarch_guest )
{
- Long delta;
- Int i, n_instrs, size, first_stmt_idx;
+ Long delta, size;
+ Int i, n_instrs, first_stmt_idx;
Addr64 guest_next;
Bool resteerOK;
DisResult dres;
}
delta += size;
- vge->len[vge->n_used-1] += size;
+ /* If vex_control.guest_max_insns is required to be < 500 and
+ each insn is at max 15 bytes long, this limit of 10000 then
+ seems reasonable since the max possible extent length will be
+ 500 * 15 == 7500. */
+ vassert(vge->len[vge->n_used-1] < 10000);
+ vge->len[vge->n_used-1]
+ = toUShort(toUInt( vge->len[vge->n_used-1] + size ));
n_instrs++;
DIP("\n");
vassert(irbb->next == NULL);
/* figure out a new delta to continue at. */
vassert(chase_into_ok(guest_next));
- delta = (ULong)(guest_next - guest_rip_start);
+ delta = guest_next - guest_rip_start;
/* we now have to start a new extent slot. */
vge->n_used++;
vassert(vge->n_used <= 3);
/* Get a byte value out of the insn stream and sign-extend to 64
bits. */
-static ULong getSDisp8 ( ULong delta )
+static Long getSDisp8 ( ULong delta )
{
return extend_s_8to64( guest_code[delta] );
}
/* Get a 16-bit value out of the insn stream and sign-extend to 64
bits. */
-static ULong getSDisp16 ( ULong delta )
+static Long getSDisp16 ( ULong delta )
{
UInt v = guest_code[delta+1]; v <<= 8;
v |= guest_code[delta+0];
/* Get a 32-bit value out of the insn stream and sign-extend to 64
bits. */
-static ULong getSDisp32 ( ULong delta )
+static Long getSDisp32 ( ULong delta )
{
UInt v = guest_code[delta+3]; v <<= 8;
v |= guest_code[delta+2]; v <<= 8;
}
/* Get a 64-bit value out of the insn stream. */
-static ULong getDisp64 ( ULong delta )
+static Long getDisp64 ( ULong delta )
{
ULong v = 0;
v |= guest_code[delta+7]; v <<= 8;
/* Note: because AMD64 doesn't allow 64-bit literals, it is an error
if this is called with size==8. Should not happen. */
-static ULong getSDisp ( Int size, ULong delta )
+static Long getSDisp ( Int size, ULong delta )
{
switch (size) {
case 4: return getSDisp32(delta);
jump table seems a bit excessive.
*/
mod_reg_rm &= 0xC7; /* is now XX000YYY */
- mod_reg_rm = or8( mod_reg_rm,
- shr8U(mod_reg_rm, 3) ); /* is now XX0XXYYY */
+ mod_reg_rm = toUChar(mod_reg_rm | (mod_reg_rm >> 3));
+ /* is now XX0XXYYY */
mod_reg_rm &= 0x1F; /* is now 000XXYYY */
switch (mod_reg_rm) {
*/
case 0x00: case 0x01: case 0x02: case 0x03:
/* ! 04 */ /* ! 05 */ case 0x06: case 0x07:
- { UChar rm = and8(mod_reg_rm, 7);
+ { UChar rm = toUChar(mod_reg_rm & 7);
DIS(buf, "%s(%s)", sorbTxt(pfx), nameIRegB(pfx,8,rm));
*len = 1;
return disAMode_copy2tmp(
*/
case 0x08: case 0x09: case 0x0A: case 0x0B:
/* ! 0C */ case 0x0D: case 0x0E: case 0x0F:
- { UChar rm = and8(mod_reg_rm, 7);
+ { UChar rm = toUChar(mod_reg_rm & 7);
Long d = getSDisp8(delta);
if (d == 0) {
DIS(buf, "%s(%s)", sorbTxt(pfx), nameIRegB(pfx,8,rm));
*/
case 0x10: case 0x11: case 0x12: case 0x13:
/* ! 14 */ case 0x15: case 0x16: case 0x17:
- { UChar rm = and8(mod_reg_rm, 7);
+ { UChar rm = toUChar(mod_reg_rm & 7);
Long d = getSDisp32(delta);
DIS(buf, "%s%lld(%s)", sorbTxt(pfx), d, nameIRegB(pfx,8,rm));
*len = 5;
= %base + (%index << scale)
*/
UChar sib = getUChar(delta);
- UChar scale = and8(shr8U(sib,6), 3);
- UChar index_r = and8(shr8U(sib,3), 7);
- UChar base_r = and8(sib, 7);
+ UChar scale = toUChar((sib >> 6) & 3);
+ UChar index_r = toUChar((sib >> 3) & 7);
+ UChar base_r = toUChar(sib & 7);
/* correct since #(R13) == 8 + #(RBP) */
Bool base_is_BPor13 = toBool(base_r == R_RBP);
Bool index_is_SP = toBool(index_r == R_RSP && 0==getRexX(pfx));
*/
case 0x0C: {
UChar sib = getUChar(delta);
- UChar scale = and8(shr8U(sib,6), 3);
- UChar index_r = and8(shr8U(sib,3), 7);
- UChar base_r = and8(sib, 7);
+ UChar scale = toUChar((sib >> 6) & 3);
+ UChar index_r = toUChar((sib >> 3) & 7);
+ UChar base_r = toUChar(sib & 7);
Long d = getSDisp8(delta+1);
if (index_r == R_RSP && 0==getRexX(pfx)) {
*/
case 0x14: {
UChar sib = getUChar(delta);
- UChar scale = and8(shr8U(sib,6), 3);
- UChar index_r = and8(shr8U(sib,3), 7);
- UChar base_r = and8(sib, 7);
+ UChar scale = toUChar((sib >> 6) & 3);
+ UChar index_r = toUChar((sib >> 3) & 7);
+ UChar base_r = toUChar(sib & 7);
Long d = getSDisp32(delta+1);
if (index_r == R_RSP && 0==getRexX(pfx)) {
jump table seems a bit excessive.
*/
mod_reg_rm &= 0xC7; /* is now XX000YYY */
- mod_reg_rm = or8( mod_reg_rm,
- shr8U(mod_reg_rm, 3) ); /* is now XX0XXYYY */
+ mod_reg_rm = toUChar(mod_reg_rm | (mod_reg_rm >> 3));
+ /* is now XX0XXYYY */
mod_reg_rm &= 0x1F; /* is now 000XXYYY */
switch (mod_reg_rm) {
case 0x04: {
/* SIB, with no displacement. */
UChar sib = getUChar(delta);
- UChar base_r = and8(sib,7);
+ UChar base_r = toUChar(sib & 7);
/* correct since #(R13) == 8 + #(RBP) */
Bool base_is_BPor13 = toBool(base_r == R_RBP);
IRTemp res64 = newTemp(Ity_I64);
IRTemp res64ss = newTemp(Ity_I64);
IRTemp shift_amt = newTemp(Ity_I8);
- UChar mask = sz==8 ? 63 : 31;
+ UChar mask = toUChar(sz==8 ? 63 : 31);
IROp op64;
switch (gregOfRM(modrm)) {
IRTemp rot_amt = newTemp(Ity_I8);
IRTemp rot_amt64 = newTemp(Ity_I8);
IRTemp oldFlags = newTemp(Ity_I64);
- UChar mask = sz==8 ? 63 : 31;
+ UChar mask = toUChar(sz==8 ? 63 : 31);
/* rot_amt = shift_expr & mask */
/* By masking the rotate amount thusly, the IR-level Shl/Shr
RDX:RAX/EDX:EAX/DX:AX/AX.
*/
static void codegen_mulL_A_D ( Int sz, Bool syned,
- IRTemp tmp, Char* tmp_txt )
+ IRTemp tmp, HChar* tmp_txt )
{
IRType ty = szToITy(sz);
IRTemp t1 = newTemp(ty);
void fp_do_op_ST_ST ( HChar* op_txt, IROp op, UInt st_src, UInt st_dst,
Bool pop_after )
{
- DIP("f%s%s st(%d), st(%d)\n", op_txt, pop_after?"p":"", st_src, st_dst );
+ DIP("f%s%s st(%u), st(%u)\n", op_txt, pop_after?"p":"", st_src, st_dst );
put_ST_UNCHECKED(
st_dst,
binop(op, get_ST(st_dst), get_ST(st_src) )
/* %rflags(Z,P,C) = UCOMI( st(0), st(i) ) */
static void fp_do_ucomi_ST0_STi ( UInt i, Bool pop_after )
{
- DIP("fucomi%s %%st(0),%%st(%d)\n", pop_after ? "p" : "", i);
+ DIP("fucomi%s %%st(0),%%st(%u)\n", pop_after ? "p" : "", i);
/* This is a bit of a hack (and isn't really right). It sets
Z,P,C,O correctly, but forces A and S to zero, whereas the Intel
documentation implies A and S are unchanged.
/* bits 5,4,3 are an opcode extension, and the modRM also
specifies an address. */
- IRTemp addr = disAMode( &len, pfx, delta, dis_buf, 0 );
- delta += len;
+ //IRTemp addr = disAMode( &len, pfx, delta, dis_buf, 0 );
+ //delta += len;
switch (gregOfRM(modrm)) {
case 0xC0 ... 0xC7: /* FLD %st(?) */
r_src = (UInt)modrm - 0xC0;
- DIP("fld %%st(%d)\n", r_src);
+ DIP("fld %%st(%u)\n", r_src);
t1 = newTemp(Ity_F64);
assign(t1, get_ST(r_src));
fp_push();
case 0xC8 ... 0xCF: /* FXCH %st(?) */
r_src = (UInt)modrm - 0xC8;
- DIP("fxch %%st(%d)\n", r_src);
+ DIP("fxch %%st(%u)\n", r_src);
t1 = newTemp(Ity_F64);
t2 = newTemp(Ity_F64);
assign(t1, get_ST(0));
/* bits 5,4,3 are an opcode extension, and the modRM also
specifies an address. */
- IROp fop;
- IRTemp addr = disAMode( &len, pfx, delta, dis_buf, 0 );
+ //IROp fop;
+ //IRTemp addr = disAMode( &len, pfx, delta, dis_buf, 0 );
delta += len;
switch (gregOfRM(modrm)) {
case 0xC8 ... 0xCF: /* FCMOVE(Z) ST(i), ST(0) */
r_src = (UInt)modrm - 0xC8;
- DIP("fcmovz %%st(%d), %%st(0)\n", r_src);
+ DIP("fcmovz %%st(%u), %%st(0)\n", r_src);
put_ST_UNCHECKED(0,
IRExpr_Mux0X(
unop(Iop_1Uto8,
case 0xD0 ... 0xD7: /* FCMOVBE ST(i), ST(0) */
r_src = (UInt)modrm - 0xD0;
- DIP("fcmovbe %%st(%d), %%st(0)\n", r_src);
+ DIP("fcmovbe %%st(%u), %%st(0)\n", r_src);
put_ST_UNCHECKED(0,
IRExpr_Mux0X(
unop(Iop_1Uto8,
case 0xD8 ... 0xDF: /* FSTP %st(0),%st(?) */
r_dst = (UInt)modrm - 0xD8;
- DIP("fstp %%st(0),%%st(%d)\n", r_dst);
+ DIP("fstp %%st(0),%%st(%u)\n", r_dst);
/* P4 manual says: "If the destination operand is a
non-empty register, the invalid-operation exception
is not generated. Hence put_ST_UNCHECKED. */
}
else
if (needNot && !all_lanes) {
- mask = sz==4 ? 0x000F : 0x00FF;
+ mask = toUShort(sz==4 ? 0x000F : 0x00FF);
putXMMReg( gregOfRexRM(pfx,rm),
binop(Iop_XorV128, mkexpr(plain), mkV128(mask)) );
}
/*IN*/ Bool (*resteerOkFn) ( Addr64 ),
/*IN*/ ULong delta,
/*IN*/ VexSubArch subarch,
- /*OUT*/ UInt* size,
+ /*OUT*/ Long* size,
/*OUT*/ Addr64* whereNext )
{
IRType ty;
IRTemp addr, /* t0, */ t1, t2, t3, t4 /*, t5, t6 */;
Int alen;
UChar opc, modrm, /*abyte,*/ pre;
- ULong d64;
+ Long d64;
HChar dis_buf[50];
Int am_sz, d_sz, n, n_prefixes;
DisResult whatNext = Dis_Continue;
&& ( /* insn[1] == 0x2D || */ insn[1] == 0x2C)) {
IRTemp rmode = newTemp(Ity_I32);
IRTemp f64lo = newTemp(Ity_F64);
- Bool r2zero = insn[1] == 0x2C;
+ Bool r2zero = toBool(insn[1] == 0x2C);
vassert(sz == 4 || sz == 8);
modrm = getUChar(delta+2);
IRTemp d0 = newTemp(Ity_I64);
IRTemp sV = newTemp(Ity_V128);
IRTemp dV = newTemp(Ity_V128);
- Bool hi = insn[1] == 0x15;
+ Bool hi = toBool(insn[1] == 0x15);
modrm = insn[2];
assign( dV, getXMMReg(gregOfRexRM(pfx,modrm)) );
assign( t1, binop(Iop_Sub64,getIReg64(R_RSP),mkU64(sz)) );
putIReg64(R_RSP, mkexpr(t1) );
storeLE( mkexpr(t1), mkU(ty,d64) );
- DIP("push%c $%lld\n", nameISize(sz), d64);
+ DIP("push%c $%lld\n", nameISize(sz), (Long)d64);
break;
case 0x9C: /* PUSHF */ {
projects / thirdparty / valgrind.git / commitdiff
