arm64: dts: morello: Fix-up cache nodes

There's no need include the CPU number in the L2 cache node names as
the names are local to the CPU nodes. The documented node name is
also just "l2-cache".

The L3 cache is not part of cpu@0/l2-cache as it is shared among all
cores. Move it to /cpus node which is the typical place for shared
caches.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20250403-dt-cpu-schema-v1-3-076be7171a85@kernel.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm/morello.dtsi
index 0bab0b3ea9693e97251f91e0d05700a6d0821da3..5bc1c725dc860b69ff7e73e35a269f4393ba18ae 100644 (file)
--- a/arch/arm64/boot/dts/arm/morello.dtsi
+++ b/arch/arm64/boot/dts/arm/morello.dtsi
@@ -44,7 +44,7 @@
                        next-level-cache = <&l2_0>;
                        clocks = <&scmi_dvfs 0>;
 
-                       l2_0: l2-cache-0 {
+                       l2_0: l2-cache {
                                compatible = "cache";
                                cache-level = <2>;
                                /* 8 ways set associative */
@@ -53,13 +53,6 @@
                                cache-sets = <2048>;
                                cache-unified;
                                next-level-cache = <&l3_0>;
-
-                               l3_0: l3-cache {
-                                       compatible = "cache";
-                                       cache-level = <3>;
-                                       cache-size = <0x100000>;
-                                       cache-unified;
-                               };
                        };
                };
 
@@ -78,7 +71,7 @@
                        next-level-cache = <&l2_1>;
                        clocks = <&scmi_dvfs 0>;
 
-                       l2_1: l2-cache-1 {
+                       l2_1: l2-cache {
                                compatible = "cache";
                                cache-level = <2>;
                                /* 8 ways set associative */
@@ -105,7 +98,7 @@
                        next-level-cache = <&l2_2>;
                        clocks = <&scmi_dvfs 1>;
 
-                       l2_2: l2-cache-2 {
+                       l2_2: l2-cache {
                                compatible = "cache";
                                cache-level = <2>;
                                /* 8 ways set associative */
@@ -132,7 +125,7 @@
                        next-level-cache = <&l2_3>;
                        clocks = <&scmi_dvfs 1>;
 
-                       l2_3: l2-cache-3 {
+                       l2_3: l2-cache {
                                compatible = "cache";
                                cache-level = <2>;
                                /* 8 ways set associative */
@@ -143,6 +136,13 @@
                                next-level-cache = <&l3_0>;
                        };
                };
+
+               l3_0: l3-cache {
+                       compatible = "cache";
+                       cache-level = <3>;
+                       cache-size = <0x100000>;
+                       cache-unified;
+               };
        };
 
        firmware {