arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces

Enable the Gigabit Ethernet Interfaces (GBETH) populated on the RZ/G3E SMARC EVK

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250702005706.1200059-5-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
index f99a09d04ddd41f876397a4c7214549850f0cadf..7faa44510d98833bef396e9f069c7c2a4fe3991f 100644 (file)
--- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
@@ -26,6 +26,8 @@
        compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047";
 
        aliases {
+               ethernet0 = &eth0;
+               ethernet1 = &eth1;
                i2c2 = &i2c2;
                mmc0 = &sdhi0;
                mmc2 = &sdhi2;
@@ -77,6 +79,24 @@
        clock-frequency = <48000000>;
 };
 
+&eth0 {
+       phy-handle = <&phy0>;
+       phy-mode = "rgmii-id";
+
+       pinctrl-0 = <&eth0_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
+&eth1 {
+       phy-handle = <&phy1>;
+       phy-mode = "rgmii-id";
+
+       pinctrl-0 = <&eth1_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
 &gpu {
        status = "okay";
        mali-supply = <&reg_vdd0p8v_others>;
@@ -102,7 +122,98 @@
        };
 };
 
+&mdio0 {
+       phy0: ethernet-phy@7 {
+               compatible = "ethernet-phy-id0022.1640",
+                            "ethernet-phy-ieee802.3-c22";
+               reg = <7>;
+               interrupts-extended = <&icu 3 IRQ_TYPE_LEVEL_LOW>;
+               rxc-skew-psec = <1400>;
+               txc-skew-psec = <1400>;
+               rxdv-skew-psec = <0>;
+               txdv-skew-psec = <0>;
+               rxd0-skew-psec = <0>;
+               rxd1-skew-psec = <0>;
+               rxd2-skew-psec = <0>;
+               rxd3-skew-psec = <0>;
+               txd0-skew-psec = <0>;
+               txd1-skew-psec = <0>;
+               txd2-skew-psec = <0>;
+               txd3-skew-psec = <0>;
+       };
+};
+
+&mdio1 {
+       phy1: ethernet-phy@7 {
+               compatible = "ethernet-phy-id0022.1640",
+                            "ethernet-phy-ieee802.3-c22";
+               reg = <7>;
+               interrupts-extended = <&icu 16 IRQ_TYPE_LEVEL_LOW>;
+               rxc-skew-psec = <1400>;
+               txc-skew-psec = <1400>;
+               rxdv-skew-psec = <0>;
+               txdv-skew-psec = <0>;
+               rxd0-skew-psec = <0>;
+               rxd1-skew-psec = <0>;
+               rxd2-skew-psec = <0>;
+               rxd3-skew-psec = <0>;
+               txd0-skew-psec = <0>;
+               txd1-skew-psec = <0>;
+               txd2-skew-psec = <0>;
+               txd3-skew-psec = <0>;
+       };
+};
+
 &pinctrl {
+       eth0_pins: eth0 {
+               clk {
+                       pinmux = <RZG3E_PORT_PINMUX(B, 1, 1)>; /* TXC */
+                       output-enable;
+               };
+
+               ctrl {
+                       pinmux = <RZG3E_PORT_PINMUX(A, 1, 1)>, /* MDC */
+                                <RZG3E_PORT_PINMUX(A, 0, 1)>, /* MDIO */
+                                <RZG3E_PORT_PINMUX(C, 2, 15)>, /* PHY_INTR (IRQ2) */
+                                <RZG3E_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
+                                <RZG3E_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
+                                <RZG3E_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
+                                <RZG3E_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
+                                <RZG3E_PORT_PINMUX(B, 0, 1)>, /* RXC */
+                                <RZG3E_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
+                                <RZG3E_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
+                                <RZG3E_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
+                                <RZG3E_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
+                                <RZG3E_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
+                                <RZG3E_PORT_PINMUX(A, 3, 1)>; /* TX_CTL */
+               };
+       };
+
+       eth1_pins: eth1 {
+               clk {
+                       pinmux = <RZG3E_PORT_PINMUX(E, 1, 1)>; /* TXC */
+                       output-enable;
+               };
+
+               ctrl {
+
+                       pinmux = <RZG3E_PORT_PINMUX(D, 1, 1)>, /* MDC */
+                                <RZG3E_PORT_PINMUX(D, 0, 1)>, /* MDIO */
+                                <RZG3E_PORT_PINMUX(F, 2, 15)>, /* PHY_INTR (IRQ15) */
+                                <RZG3E_PORT_PINMUX(F, 1, 1)>, /* RXD3 */
+                                <RZG3E_PORT_PINMUX(F, 0, 1)>, /* RXD2 */
+                                <RZG3E_PORT_PINMUX(E, 7, 1)>, /* RXD1 */
+                                <RZG3E_PORT_PINMUX(E, 6, 1)>, /* RXD0 */
+                                <RZG3E_PORT_PINMUX(E, 0, 1)>, /* RXC */
+                                <RZG3E_PORT_PINMUX(D, 2, 1)>, /* RX_CTL */
+                                <RZG3E_PORT_PINMUX(E, 5, 1)>, /* TXD3 */
+                                <RZG3E_PORT_PINMUX(E, 4, 1)>, /* TXD2 */
+                                <RZG3E_PORT_PINMUX(E, 3, 1)>, /* TXD1 */
+                                <RZG3E_PORT_PINMUX(E, 2, 1)>, /* TXD0 */
+                                <RZG3E_PORT_PINMUX(D, 3, 1)>; /* TX_CTL */
+               };
+       };
+
        i2c2_pins: i2c {
                pinmux = <RZG3E_PORT_PINMUX(3, 4, 1)>, /* SCL2 */
                         <RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */