lspci: Decode Physical Layer 16 GT/s and 32 GT/s extended capability registers

diff --git a/lib/header.h b/lib/header.h
index 0827ac0d4b739f16ff9fce39a8531707dcd8aaf2..3dc43b3d7b9e6fe67f2479b5abe68aefecb4c8ef 100644 (file)
--- a/lib/header.h
+++ b/lib/header.h
@@ -1367,6 +1367,46 @@
 #define PCI_SEC_LANE_ERR       8       /* Lane Error status register */
 #define PCI_SEC_LANE_EQU_CTRL  12      /* Lane Equalization control register */
 
+/* Physical Layer 16 GT/s Extended Capability */
+#define PCI_16GT_CAP           0x04    /* 16 GT/s Capabilities Register */
+#define PCI_16GT_CTL           0x08    /* 16 GT/s Control Register */
+#define PCI_16GT_STATUS                0x0C    /* 16 GT/s Status Register */
+#define  PCI_16GT_STATUS_EQU_COMP      0x0001  /* Equalization 16 GT/s Complete */
+#define  PCI_16GT_STATUS_EQU_PHASE1    0x0002  /* Equalization 16 GT/s Phase 1 Successful */
+#define  PCI_16GT_STATUS_EQU_PHASE2    0x0004  /* Equalization 16 GT/s Phase 2 Successful */
+#define  PCI_16GT_STATUS_EQU_PHASE3    0x0008  /* Equalization 16 GT/s Phase 3 Successful */
+#define  PCI_16GT_STATUS_EQU_REQ       0x0010  /* Link Equalization Request 16 GT/s */
+#define PCI_16GT_LDPM          0x10    /* 16 GT/s Local Data Parity Mismatch Status Register */
+#define PCI_16GT_FRDPM         0x14    /* 16 GT/s First Retimer Data Parity Mismatch Status Register */
+#define PCI_16GT_SRDPM         0x18    /* 16 GT/s Second Retimer Data Parity Mismatch Status Register */
+
+/* Physical Layer 32 GT/s Extended Capability */
+#define PCI_32GT_CAP           0x04    /* 32 GT/s Capabilities Register */
+#define  PCI_32GT_CAP_EQU_BYPASS       0x0001  /* Equalization bypass to highest rate Supported */
+#define  PCI_32GT_CAP_NO_EQU_NEEDED    0x0002  /* No Equalization Needed Supported */
+#define  PCI_32GT_CAP_MOD_TS_MODE_0    0x0100  /* Modified TS Usage Mode 0 Supported - PCI Express */
+#define  PCI_32GT_CAP_MOD_TS_MODE_1    0x0200  /* Modified TS Usage Mode 1 Supported - Training Set Message */
+#define  PCI_32GT_CAP_MOD_TS_MODE_2    0x0400  /* Modified TS Usage Mode 2 Supported - Alternate Protocol */
+#define PCI_32GT_CTL           0x08    /* 32 GT/s Control Register */
+#define  PCI_32GT_CTL_EQU_BYPASS_DIS   0x1     /* Equalization bypass to highest rate Disable */
+#define  PCI_32GT_CTL_NO_EQU_NEEDED_DIS        0x2     /* No Equalization Needed Disable */
+#define  PCI_32GT_CTL_MOD_TS_MODE(x) (((x) >> 8) & 0x7)        /* Modified TS Usage Mode Selected */
+#define PCI_32GT_STATUS                0x0C    /* 32 GT/s Status Register */
+#define  PCI_32GT_STATUS_EQU_COMP      0x0001  /* Equalization 32 GT/s Complete */
+#define  PCI_32GT_STATUS_EQU_PHASE1    0x0002  /* Equalization 32 GT/s Phase 1 Successful */
+#define  PCI_32GT_STATUS_EQU_PHASE2    0x0004  /* Equalization 32 GT/s Phase 2 Successful */
+#define  PCI_32GT_STATUS_EQU_PHASE3    0x0008  /* Equalization 32 GT/s Phase 3 Successful */
+#define  PCI_32GT_STATUS_EQU_REQ       0x0010  /* Link Equalization Request 32 GT/s */
+#define  PCI_32GT_STATUS_MOD_TS                0x0020  /* Modified TS Received */
+#define  PCI_32GT_STATUS_RCV_ENH_LINK(x) (((x) >> 6) & 0x3)    /* Received Enhanced Link Behavior Control */
+#define  PCI_32GT_STATUS_TX_PRE_ON     0x0100  /* Transmitter Precoding On */
+#define  PCI_32GT_STATUS_TX_PRE_REQ    0x0200  /* Transmitter Precoding Request */
+#define  PCI_32GT_STATUS_NO_EQU        0x0400  /* No Equalization Needed Received */
+#define PCI_32GT_RXMODTS1      0x10    /* Received Modified TS Data 1 Register */
+#define PCI_32GT_RXMODTS2      0x14    /* Received Modified TS Data 2 Register */
+#define PCI_32GT_TXMODTS1      0x18    /* Transmitted Modified TS Data 1 Register */
+#define PCI_32GT_TXMODTS2      0x1C    /* Transmitted Modified TS Data 2 Register */
+
 /* Process Address Space ID */
 #define PCI_PASID_CAP          0x04    /* PASID feature register */
 #define  PCI_PASID_CAP_EXEC    0x02    /* Exec permissions Supported */

diff --git a/ls-ecaps.c b/ls-ecaps.c
index e817180889c282d5053be6e2bb7e8e712d084b5c..a725aedff0319c4f079f7c523996458386b48e28 100644 (file)
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -733,6 +733,88 @@ cap_lmr(struct device *d, int where)
          FLAG(port_status, PCI_LMR_PORT_STS_SOFT_READY));
 }
 
+static void
+cap_phy_16gt(struct device *d, int where)
+{
+  printf("Physical Layer 16.0 GT/s\n");
+
+  if (verbose < 2)
+    return;
+
+  if (!config_fetch(d, where + PCI_16GT_CAP, 0x18)) {
+    printf("\t\t<unreadable>\n");
+    return;
+  }
+
+  u32 status = get_conf_long(d, where + PCI_16GT_STATUS);
+
+  printf("\t\tPhy16Sta: EquComplete%c EquPhase1%c EquPhase2%c EquPhase3%c LinkEquRequest%c\n",
+         FLAG(status, PCI_16GT_STATUS_EQU_COMP),
+         FLAG(status, PCI_16GT_STATUS_EQU_PHASE1),
+         FLAG(status, PCI_16GT_STATUS_EQU_PHASE2),
+         FLAG(status, PCI_16GT_STATUS_EQU_PHASE3),
+         FLAG(status, PCI_16GT_STATUS_EQU_REQ));
+}
+
+static void
+cap_phy_32gt(struct device *d, int where)
+{
+  static const char * const mod_ts_modes[] = {
+    "PCI Express",
+    "Training Set Messages",
+    "Alternate Protocol Negotiation"
+  };
+  static const char * const enh_link_ctl[] = {
+    "Full Equalization required",
+    "Equalization bypass to highest rate support",
+    "No Equalization Needed",
+    "Modified TS1/TS2 Ordered Sets supported"
+  };
+  char buf[48];
+
+  printf("Physical Layer 32.0 GT/s\n");
+
+  if (verbose < 2)
+    return;
+
+  if (!config_fetch(d, where + PCI_32GT_CAP, 0x1C)) {
+    printf("\t\t<unreadable>\n");
+    return;
+  }
+
+  u32 cap = get_conf_long(d, where + PCI_32GT_CAP);
+  u32 ctl = get_conf_long(d, where + PCI_32GT_CTL);
+  u32 status = get_conf_long(d, where + PCI_32GT_STATUS);
+
+  printf("\t\tPhy32Cap: EqualizationBypass%c NoEqualizationNeeded%c\n"
+         "\t\t\t  ModTsMode0%c ModTsMode1%c ModTsMode2%c\n",
+         FLAG(cap, PCI_32GT_CAP_EQU_BYPASS),
+         FLAG(cap, PCI_32GT_CAP_NO_EQU_NEEDED),
+         FLAG(cap, PCI_32GT_CAP_MOD_TS_MODE_0),
+         FLAG(cap, PCI_32GT_CAP_MOD_TS_MODE_1),
+         FLAG(cap, PCI_32GT_CAP_MOD_TS_MODE_2));
+
+  printf("\t\tPhy32Ctl: EqualizationBypassDis%c NoEqualizationNeededDis%c\n"
+         "\t\t\t  Modified TS Usage Mode: %s\n",
+         FLAG(ctl, PCI_32GT_CTL_EQU_BYPASS_DIS),
+         FLAG(ctl, PCI_32GT_CTL_NO_EQU_NEEDED_DIS),
+         TABLE(mod_ts_modes, PCI_32GT_CTL_MOD_TS_MODE(ctl), buf));
+
+  printf("\t\tPhy32Sta: EquComplete%c EquPhase1%c EquPhase2%c EquPhase3%c LinkEquRequest%c\n"
+         "\t\t\t  Received Enhanced Link Behavior Control: %s\n"
+         "\t\t\t  ModTsRecv%c TxPrecodeOn%c TxPrecodeReq%c NoEqualizationNeededRecv%c\n",
+         FLAG(status, PCI_32GT_STATUS_EQU_COMP),
+         FLAG(status, PCI_32GT_STATUS_EQU_PHASE1),
+         FLAG(status, PCI_32GT_STATUS_EQU_PHASE2),
+         FLAG(status, PCI_32GT_STATUS_EQU_PHASE3),
+         FLAG(status, PCI_32GT_STATUS_EQU_REQ),
+         TABLE(enh_link_ctl, PCI_32GT_STATUS_RCV_ENH_LINK(status), buf),
+         FLAG(status, PCI_32GT_STATUS_MOD_TS),
+         FLAG(status, PCI_32GT_STATUS_TX_PRE_ON),
+         FLAG(status, PCI_32GT_STATUS_TX_PRE_REQ),
+         FLAG(status, PCI_32GT_STATUS_NO_EQU));
+}
+
 static void
 cxl_range(u64 base, u64 size, int n)
 {
@@ -1840,7 +1922,7 @@ show_ext_caps(struct device *d, int type)
            printf("Data Link Feature <?>\n");
            break;
          case PCI_EXT_CAP_ID_16GT:
-           printf("Physical Layer 16.0 GT/s <?>\n");
+           cap_phy_16gt(d, where);
            break;
          case PCI_EXT_CAP_ID_LMR:
            cap_lmr(d, where);
@@ -1851,9 +1933,9 @@ show_ext_caps(struct device *d, int type)
          case PCI_EXT_CAP_ID_NPEM:
            printf("Native PCIe Enclosure Management <?>\n");
            break;
-      case PCI_EXT_CAP_ID_32GT:
-           printf("Physical Layer 32.0 GT/s <?>\n");
-        break;
+         case PCI_EXT_CAP_ID_32GT:
+           cap_phy_32gt(d, where);
+           break;
          case PCI_EXT_CAP_ID_DOE:
            cap_doe(d, where);
            break;

diff --git a/setpci.c b/setpci.c
index 7b7baea6069096b8ced780167fd884900b277b19..e359ffdf9fadd3fd0c8cbb78f9ed0f946ead416b 100644 (file)
--- a/setpci.c
+++ b/setpci.c
@@ -396,6 +396,7 @@ static const struct reg_name pci_reg_names[] = {
   { 0x20027,   0, 0, 0x0, "ECAP_LMR" },
   { 0x20028,   0, 0, 0x0, "ECAP_HIER_ID" },
   { 0x20029,   0, 0, 0x0, "ECAP_NPEM" },
+  { 0x2002a,   0, 0, 0x0, "ECAP_32GT" },
   { 0x20030,   0, 0, 0x0, "ECAP_IDE" },
   {       0,    0, 0, 0x0, NULL }
 };