arm64: dts: qcom: sm8550: Use the header with DSI phy clock IDs

Use the header with DSI phy clock IDs to make code more readable.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-23-73b482a6dd02@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index f78d5292c5dd5ec88c8deb0ca6e5078511ac52b7..a2732e04896e2f6dcdcd019d90d23731ad0d15a7 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3,6 +3,7 @@
  * Copyright (c) 2022, Linaro Limited
  */
 
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
 #include <dt-bindings/clock/qcom,sm8550-camcc.h>
@@ -3554,8 +3555,8 @@
 
                                assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
                                                  <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
-                               assigned-clock-parents = <&mdss_dsi0_phy 0>,
-                                                        <&mdss_dsi0_phy 1>;
+                               assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+                                                        <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
 
                                operating-points-v2 = <&mdss_dsi_opp_table>;
 
@@ -3649,8 +3650,8 @@
 
                                assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
                                                  <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
-                               assigned-clock-parents = <&mdss_dsi1_phy 0>,
-                                                        <&mdss_dsi1_phy 1>;
+                               assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
+                                                        <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>;
 
                                operating-points-v2 = <&mdss_dsi_opp_table>;
 
@@ -3708,10 +3709,10 @@
                                 <&bi_tcxo_ao_div2>,
                                 <&gcc GCC_DISP_AHB_CLK>,
                                 <&sleep_clk>,
-                                <&mdss_dsi0_phy 0>,
-                                <&mdss_dsi0_phy 1>,
-                                <&mdss_dsi1_phy 0>,
-                                <&mdss_dsi1_phy 1>,
+                                <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+                                <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
+                                <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
+                                <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,
                                 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
                                 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
                                 <0>, /* dp1 */