Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d75296d982c1fb5292ca1cda1cf88040b8665d01..d6dde8d33f56e51dd36434923fb9a84ef818ab03 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,69 @@
+2020-08-04  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * config/aarch64/aarch64-protos.h (aarch64_indirect_call_asm):
+       New declaration.
+       * config/aarch64/aarch64.c (aarch64_regno_regclass): Handle new
+       stub registers class.
+       (aarch64_class_max_nregs): Likewise.
+       (aarch64_register_move_cost): Likewise.
+       (aarch64_sls_shared_thunks): Global array to store stub labels.
+       (aarch64_sls_emit_function_stub): New.
+       (aarch64_create_blr_label): New.
+       (aarch64_sls_emit_blr_function_thunks): New.
+       (aarch64_sls_emit_shared_blr_thunks): New.
+       (aarch64_asm_file_end): New.
+       (aarch64_indirect_call_asm): New.
+       (TARGET_ASM_FILE_END): Use aarch64_asm_file_end.
+       (TARGET_ASM_FUNCTION_EPILOGUE): Use
+       aarch64_sls_emit_blr_function_thunks.
+       * config/aarch64/aarch64.h (STB_REGNUM_P): New.
+       (enum reg_class): Add STUB_REGS class.
+       (machine_function): Introduce `call_via` array for
+       function-local stub labels.
+       * config/aarch64/aarch64.md (*call_insn, *call_value_insn): Use
+       aarch64_indirect_call_asm to emit code when hardening BLR
+       instructions.
+       * config/aarch64/constraints.md (Ucr): New constraint
+       representing registers for indirect calls.  Is GENERAL_REGS
+       usually, and STUB_REGS when hardening BLR instruction against
+       SLS.
+       * config/aarch64/predicates.md (aarch64_general_reg): STUB_REGS class
+       is also a general register.
+
+2020-08-04  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * config/aarch64/aarch64-protos.h (aarch64_sls_barrier): New.
+       * config/aarch64/aarch64.c (aarch64_output_casesi): Emit
+       speculation barrier after BR instruction if needs be.
+       (aarch64_trampoline_init): Handle ptr_mode value & adjust size
+       of code copied.
+       (aarch64_sls_barrier): New.
+       (aarch64_asm_trampoline_template): Add needed barriers.
+       * config/aarch64/aarch64.h (AARCH64_ISA_SB): New.
+       (TARGET_SB): New.
+       (TRAMPOLINE_SIZE): Account for barrier.
+       * config/aarch64/aarch64.md (indirect_jump, *casesi_dispatch,
+       simple_return, *do_return, *sibcall_insn, *sibcall_value_insn):
+       Emit barrier if needs be, also account for possible barrier using
+       "sls_length" attribute.
+       (sls_length): New attribute.
+       (length): Determine default using any non-default sls_length
+       value.
+
+2020-08-04  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * config/aarch64/aarch64-protos.h (aarch64_harden_sls_retbr_p):
+       New.
+       (aarch64_harden_sls_blr_p): New.
+       * config/aarch64/aarch64.c (enum aarch64_sls_hardening_type):
+       New.
+       (aarch64_harden_sls_retbr_p): New.
+       (aarch64_harden_sls_blr_p): New.
+       (aarch64_validate_sls_mitigation): New.
+       (aarch64_override_options): Parse options for SLS mitigation.
+       * config/aarch64/aarch64.opt (-mharden-sls): New option.
+       * doc/invoke.texi: Document new option.
+
 2020-08-03  Jonathan Wakely  <jwakely@redhat.com>
 
        Backported from master:

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index f01da8770ae83552eee2c077653b360b1268158d..3a7230a5cf250067083ccb32f217807069bc3a93 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200804
+20200805

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 2fd9dfecbb9f2f45eaa4d3b977f34eb56e7ab53f..2142682e727c87ab49368c333d32dbdc60190df5 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,17 @@
+2020-08-04  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * gcc.target/aarch64/sls-mitigation/sls-miti-blr-bti.c: New test.
+       * gcc.target/aarch64/sls-mitigation/sls-miti-blr.c: New test.
+
+2020-08-04  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * gcc.target/aarch64/sls-mitigation/sls-miti-retbr.c: New test.
+       * gcc.target/aarch64/sls-mitigation/sls-miti-retbr-pacret.c:
+       New test.
+       * gcc.target/aarch64/sls-mitigation/sls-mitigation.exp: New file.
+       * lib/target-supports.exp (check_effective_target_aarch64_asm_sb_ok):
+       New proc.
+
 2020-08-01  Iain Buclaw  <ibuclaw@gdcproject.org>
 
        Backported from master: