drm/amd/pm: Add message control for SMUv14

Initialize smu message control in SMUv14 SOCs.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
index ba895ca4f3e6120e613e4538503596164bf0459f..9c15fccac2b80582bac269db0ef79ce029f02066 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
@@ -1740,6 +1740,22 @@ static void smu_v14_0_0_set_smu_mailbox_registers(struct smu_context *smu)
        smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
 }
 
+static void smu_v14_0_0_init_msg_ctl(struct smu_context *smu)
+{
+       struct amdgpu_device *adev = smu->adev;
+       struct smu_msg_ctl *ctl = &smu->msg_ctl;
+
+       ctl->smu = smu;
+       mutex_init(&ctl->lock);
+       ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
+       ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
+       ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
+       ctl->config.num_arg_regs = 1;
+       ctl->ops = &smu_msg_v1_ops;
+       ctl->default_timeout = adev->usec_timeout * 20;
+       ctl->message_map = smu_v14_0_0_message_map;
+}
+
 void smu_v14_0_0_set_ppt_funcs(struct smu_context *smu)
 {
 
@@ -1750,4 +1766,5 @@ void smu_v14_0_0_set_ppt_funcs(struct smu_context *smu)
        smu->is_apu = true;
 
        smu_v14_0_0_set_smu_mailbox_registers(smu);
+       smu_v14_0_0_init_msg_ctl(smu);
 }

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
index b1fee26d989a336b2102ce5d5f4194fe6ed5bdf0..5bf10555effd9c24ea3e7118ecaa94bcc86bd1e1 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
@@ -2120,6 +2120,22 @@ static void smu_v14_0_2_set_smu_mailbox_registers(struct smu_context *smu)
        smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_54);
 }
 
+static void smu_v14_0_2_init_msg_ctl(struct smu_context *smu)
+{
+       struct amdgpu_device *adev = smu->adev;
+       struct smu_msg_ctl *ctl = &smu->msg_ctl;
+
+       ctl->smu = smu;
+       mutex_init(&ctl->lock);
+       ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_66);
+       ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_90);
+       ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_82);
+       ctl->config.num_arg_regs = 1;
+       ctl->ops = &smu_msg_v1_ops;
+       ctl->default_timeout = adev->usec_timeout * 20;
+       ctl->message_map = smu_v14_0_2_message_map;
+}
+
 static ssize_t smu_v14_0_2_get_gpu_metrics(struct smu_context *smu,
                                           void **table)
 {
@@ -2866,4 +2882,5 @@ void smu_v14_0_2_set_ppt_funcs(struct smu_context *smu)
        smu->pwr_src_map = smu_v14_0_2_pwr_src_map;
        smu->workload_map = smu_v14_0_2_workload_map;
        smu_v14_0_2_set_smu_mailbox_registers(smu);
+       smu_v14_0_2_init_msg_ctl(smu);
 }