- description: Main GMAC registers
- description: GMAC PHY mode control register
+ nxp,phy-sel:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to the GPR syscon node
+ - description: offset of PHY selection register
+ description:
+ This phandle points to the GMAC_0_CTRL_STS register which controls the
+ GMAC_0 configuration options. The register lets you select the PHY
+ interface and the PHY mode. It also controls if the FTM_0 or FTM_1
+ FlexTimer Modules connect to GMAC_0.
+
interrupts:
maxItems: 1
compatible = "nxp,s32g2-dwmac";
reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */
<0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */
+ nxp,phy-sel = <&gpr 0x4>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";