]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
[ARM] Add ACLE intrinsics vqrdmlah and vqrdmlsh
authormwahab <mwahab@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 16 Dec 2015 12:16:13 +0000 (12:16 +0000)
committermwahab <mwahab@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 16 Dec 2015 12:16:13 +0000 (12:16 +0000)
* config/arm/arm_neon.h (vqrdmlah_s16, vqrdmlah_s32): New.
(vqrdmlahq_s16, vqrdmlahq_s32): New.
(vqrdmlsh_s16, vqrdmlsh_s32): New.
(vqrdmlahq_s16, vqrdmlshq_s32): New.
* config/arm/arm_neon_builtins.def: Add "vqrdmlah" and "vqrdmlsh".

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231685 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/arm/arm_neon.h
gcc/config/arm/arm_neon_builtins.def

index a28614cb5e8248c27c8fb67cd48940a3fda539b0..3a6df36a6def35e339e51b233f8023bd5b647c3b 100644 (file)
@@ -1,3 +1,11 @@
+2015-12-16  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * config/arm/arm_neon.h (vqrdmlah_s16, vqrdmlah_s32): New.
+       (vqrdmlahq_s16, vqrdmlahq_s32): New.
+       (vqrdmlsh_s16, vqrdmlsh_s32): New.
+       (vqrdmlahq_s16, vqrdmlshq_s32): New.
+       * config/arm/arm_neon_builtins.def: Add "vqrdmlah" and "vqrdmlsh".
+
 2015-12-16  Matthew Wahab  <matthew.wahab@arm.com>
 
        * doc/sourcebuild.texi (ARM-specific attributes): Add
index 0a33d21f2fcf8a1074fb62e89f4418295d446db5..b617f80d467423225d0eee4ab1ae9524100424c2 100644 (file)
@@ -1158,6 +1158,56 @@ vqrdmulhq_s32 (int32x4_t __a, int32x4_t __b)
   return (int32x4_t)__builtin_neon_vqrdmulhv4si (__a, __b);
 }
 
+#ifdef __ARM_FEATURE_QRDMX
+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+vqrdmlah_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
+{
+  return (int16x4_t)__builtin_neon_vqrdmlahv4hi (__a, __b, __c);
+}
+
+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+vqrdmlah_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
+{
+  return (int32x2_t)__builtin_neon_vqrdmlahv2si (__a, __b, __c);
+}
+
+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+vqrdmlahq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
+{
+  return (int16x8_t)__builtin_neon_vqrdmlahv8hi (__a, __b, __c);
+}
+
+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+vqrdmlahq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
+{
+  return (int32x4_t)__builtin_neon_vqrdmlahv4si (__a, __b, __c);
+}
+
+__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+vqrdmlsh_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
+{
+  return (int16x4_t)__builtin_neon_vqrdmlshv4hi (__a, __b, __c);
+}
+
+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+vqrdmlsh_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
+{
+  return (int32x2_t)__builtin_neon_vqrdmlshv2si (__a, __b, __c);
+}
+
+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+vqrdmlshq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
+{
+  return (int16x8_t)__builtin_neon_vqrdmlshv8hi (__a, __b, __c);
+}
+
+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+vqrdmlshq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
+{
+  return (int32x4_t)__builtin_neon_vqrdmlshv4si (__a, __b, __c);
+}
+#endif
+
 __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
 vmull_s8 (int8x8_t __a, int8x8_t __b)
 {
index 0b719df760747af7642bd14ab14a9b2144d43359..8d5c0cabc1fd51a41d12c581483e1f6311ea1f9a 100644 (file)
@@ -45,6 +45,8 @@ VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si)
 VAR4 (BINOP, vqrdmulh, v4hi, v2si, v8hi, v4si)
 VAR2 (TERNOP, vqdmlal, v4hi, v2si)
 VAR2 (TERNOP, vqdmlsl, v4hi, v2si)
+VAR4 (TERNOP, vqrdmlah, v4hi, v2si, v8hi, v4si)
+VAR4 (TERNOP, vqrdmlsh, v4hi, v2si, v8hi, v4si)
 VAR3 (BINOP, vmullp, v8qi, v4hi, v2si)
 VAR3 (BINOP, vmulls, v8qi, v4hi, v2si)
 VAR3 (BINOP, vmullu, v8qi, v4hi, v2si)