This patch adds "dts-5.10" directory to use backported drivers.
There are several specification changes in the new drivers, so there
are some compatibility issues in using dts/dtsi files for 5.4.
The old DTS files are moved to "dts-5.4", so their corresponding
kernel version is obvious as well.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[change "dts" to "dts-5.4", adjust Makefile]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl838x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "realtek,rtl838x-soc";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <20>;
+
+ mode {
+ label = "reset";
+ gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+};
+
+&gpio0 {
+ indirect-access-bus-id = <0>;
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(8, 1, internal)
+ SWITCH_PORT(9, 2, internal)
+ SWITCH_PORT(10, 3, internal)
+ SWITCH_PORT(11, 4, internal)
+ SWITCH_PORT(12, 5, internal)
+ SWITCH_PORT(13, 6, internal)
+ SWITCH_PORT(14, 7, internal)
+ SWITCH_PORT(15, 8, internal)
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_netgear_gigabit.dtsi"
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x00e0000>;
+ read-only;
+ };
+
+ partition@e0000 {
+ label = "u-boot-env";
+ reg = <0x00e0000 0x0010000>;
+ read-only;
+ };
+
+ partition@f0000 {
+ label = "u-boot-env2";
+ reg = <0x00f0000 0x0010000>;
+ };
+
+ partition@100000 {
+ label = "jffs";
+ reg = <0x0100000 0x0100000>;
+ read-only;
+ };
+
+ partition@200000 {
+ label = "jffs2";
+ reg = <0x0200000 0x0100000>;
+ read-only;
+ };
+
+ partition@300000 {
+ label = "firmware";
+ compatible = "openwrt,uimage", "denx,uimage";
+ openwrt,ih-magic = <0x4e474520>;
+ reg = <0x0300000 0x0e80000>;
+ };
+
+ partition@1180000 {
+ label = "runtime2";
+ reg = <0x1180000 0x0e80000>;
+ read-only;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_netgear_gigabit.dtsi"
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x00e0000>;
+ read-only;
+ };
+
+ partition@e0000 {
+ label = "u-boot-env";
+ reg = <0x00e0000 0x0010000>;
+ read-only;
+ };
+
+ partition@f0000 {
+ label = "u-boot-env2";
+ reg = <0x00f0000 0x0010000>;
+ };
+
+ partition@100000 {
+ label = "jffs";
+ reg = <0x0100000 0x0100000>;
+ read-only;
+ };
+
+ partition@200000 {
+ label = "jffs2";
+ reg = <0x0200000 0x0100000>;
+ read-only;
+ };
+
+ partition@300000 {
+ label = "firmware";
+ compatible = "openwrt,uimage", "denx,uimage";
+ openwrt,ih-magic = <0x4e474335>;
+ reg = <0x0300000 0x0e80000>;
+ };
+
+ partition@1180000 {
+ label = "runtime2";
+ reg = <0x1180000 0x0e80000>;
+ read-only;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_netgear_gigabit_1xx.dtsi"
+
+/ {
+ compatible = "netgear,gs108t-v3", "realtek,rtl838x-soc";
+ model = "Netgear GS108T v3";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_netgear_gigabit_1xx.dtsi"
+
+/ {
+ compatible = "netgear,gs110tpp-v1", "realtek,rtl838x-soc";
+ model = "Netgear GS110TPP v1";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_netgear_gigabit_3xx.dtsi"
+
+/ {
+ compatible = "netgear,gs308t-v1", "realtek,rtl838x-soc";
+ model = "Netgear GS308T v1";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_netgear_gigabit_3xx.dtsi"
+
+/ {
+ compatible = "netgear,gs310tp-v1", "realtek,rtl838x-soc";
+ model = "Netgear GS310TP v1";
+
+};
+
+&mdio {
+ INTERNAL_PHY(24)
+ INTERNAL_PHY(26)
+};
+
+&switch0 {
+ ports {
+ SWITCH_SFP_PORT(24, 9, rgmii-id)
+ SWITCH_SFP_PORT(26, 10, rgmii-id)
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_zyxel_gs1900.dtsi"
+
+/ {
+ compatible = "zyxel,gs1900-10hp", "realtek,rtl838x-soc";
+ model = "ZyXEL GS1900-10HP Switch";
+
+ /* i2c of the left SFP cage: port 9 */
+ i2c0: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp0: sfp-p9 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* i2c of the right SFP cage: port 10 */
+ i2c1: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp1: sfp-p10 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&mdio {
+ INTERNAL_PHY(24)
+ INTERNAL_PHY(26)
+};
+
+&switch0 {
+ ports {
+ port@24 {
+ reg = <24>;
+ label = "lan9";
+ phy-mode = "1000base-x";
+ managed = "in-band-status";
+ sfp = <&sfp0>;
+ };
+
+ port@26 {
+ reg = <26>;
+ label = "lan10";
+ phy-mode = "1000base-x";
+ managed = "in-band-status";
+ sfp = <&sfp1>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_zyxel_gs1900.dtsi"
+
+/ {
+ compatible = "zyxel,gs1900-8", "realtek,rtl838x-soc";
+ model = "ZyXEL GS1900-8 Switch";
+};
+
+&gpio1 {
+ /delete-node/ poe_enable;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_zyxel_gs1900.dtsi"
+
+/ {
+ compatible = "zyxel,gs1900-8hp-v1", "realtek,rtl838x-soc";
+ model = "ZyXEL GS1900-8HP v1 Switch";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_zyxel_gs1900.dtsi"
+
+/ {
+ compatible = "zyxel,gs1900-8hp-v2", "realtek,rtl838x-soc";
+ model = "ZyXEL GS1900-8HP v2 Switch";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl838x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ led-boot = &led_sys;
+ led-failsafe = &led_sys;
+ led-running = &led_sys;
+ led-upgrade = &led_sys;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ gpio1: rtl8231-gpio {
+ status = "okay";
+
+ poe_enable {
+ gpio-hog;
+ gpios = <13 0>;
+ output-high;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <20>;
+
+ reset {
+ label = "reset";
+ gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_sys: sys {
+ label = "green:sys";
+ gpios = <&gpio0 47 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "u-boot-env";
+ reg = <0x40000 0x10000>;
+ read-only;
+ };
+ partition@50000 {
+ label = "u-boot-env2";
+ reg = <0x50000 0x10000>;
+ };
+ partition@60000 {
+ label = "jffs";
+ reg = <0x60000 0x100000>;
+ };
+ partition@160000 {
+ label = "jffs2";
+ reg = <0x160000 0x100000>;
+ };
+ partition@b260000 {
+ label = "firmware";
+ reg = <0x260000 0x6d0000>;
+ compatible = "openwrt,uimage", "denx,uimage";
+ openwrt,ih-magic = <0x83800000>;
+ };
+ partition@930000 {
+ label = "runtime2";
+ reg = <0x930000 0x6d0000>;
+ };
+ };
+ };
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(8, 1, internal)
+ SWITCH_PORT(9, 2, internal)
+ SWITCH_PORT(10, 3, internal)
+ SWITCH_PORT(11, 4, internal)
+ SWITCH_PORT(12, 5, internal)
+ SWITCH_PORT(13, 6, internal)
+ SWITCH_PORT(14, 7, internal)
+ SWITCH_PORT(15, 8, internal)
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl838x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "allnet,all-sg8208m", "realtek,rtl838x-soc";
+ model = "ALLNET ALL-SG8208M";
+
+ aliases {
+ led-boot = &led_sys;
+ led-failsafe = &led_sys;
+ led-running = &led_sys;
+ led-upgrade = &led_sys;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <20>;
+
+ reset {
+ label = "reset";
+ gpios = <&gpio0 67 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_sys: sys {
+ label = "green:sys";
+ gpios = <&gpio0 47 GPIO_ACTIVE_HIGH>;
+ };
+ // GPIO 25: power on/off all port leds
+ };
+};
+
+&gpio0 {
+ indirect-access-bus-id = <0>;
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "u-boot-env";
+ reg = <0x80000 0x10000>;
+ read-only;
+ };
+
+ partition@90000 {
+ label = "u-boot-env2";
+ reg = <0x90000 0x10000>;
+ };
+
+ partition@a0000 {
+ label = "jffs";
+ reg = <0xa0000 0x100000>;
+ };
+
+ partition@1a0000 {
+ label = "jffs2";
+ reg = <0x1a0000 0x100000>;
+ };
+
+ partition@2a0000 {
+ label = "firmware";
+ reg = <0x2a0000 0xd60000>;
+ compatible = "openwrt,uimage", "denx,uimage";
+ openwrt,ih-magic = <0x00000006>;
+ };
+ };
+ };
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(8, 1, internal)
+ SWITCH_PORT(9, 2, internal)
+ SWITCH_PORT(10, 3, internal)
+ SWITCH_PORT(11, 4, internal)
+ SWITCH_PORT(12, 5, internal)
+ SWITCH_PORT(13, 6, internal)
+ SWITCH_PORT(14, 7, internal)
+ SWITCH_PORT(15, 8, internal)
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "d-link,dgs-1210-10p", "realtek,rtl838x-soc";
+ model = "D-Link DGS-1210-10P";
+
+ aliases {
+ led-boot = &led_power;
+ led-failsafe = &led_power;
+ led-running = &led_power;
+ led-upgrade = &led_power;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_power: power {
+ // GPIO 24 seems to provide power to the leds
+ label = "green:power";
+ gpios = <&gpio0 47 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <20>;
+
+ mode {
+ label = "reset";
+ gpios = <&gpio0 94 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+};
+
+
+&gpio0 {
+ indirect-access-bus-id = <0>;
+};
+
+&spi0 {
+ status = "okay";
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x00000000 0x80000>;
+ read-only;
+ };
+ partition@80000 {
+ label = "u-boot-env";
+ reg = <0x00080000 0x40000>;
+ read-only;
+ };
+ partition@c0000 {
+ label = "u-boot-env2";
+ reg = <0x000c0000 0x40000>;
+ };
+ partition@280000 {
+ label = "firmware";
+ compatible = "denx,uimage";
+ reg = <0x00100000 0xd80000>;
+ };
+ partition@be80000 {
+ label = "kernel2";
+ reg = <0x00e80000 0x180000>;
+ };
+ partition@1000000 {
+ label = "sysinfo";
+ reg = <0x01000000 0x40000>;
+ };
+ partition@1040000 {
+ label = "rootfs2";
+ reg = <0x01040000 0xc00000>;
+ };
+ partition@1c40000 {
+ label = "jffs2";
+ reg = <0x01c40000 0x3c0000>;
+ };
+ };
+ };
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+ INTERNAL_PHY(24)
+ INTERNAL_PHY(26)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(8, 1, internal)
+ SWITCH_PORT(9, 2, internal)
+ SWITCH_PORT(10, 3, internal)
+ SWITCH_PORT(11, 4, internal)
+ SWITCH_PORT(12, 5, internal)
+ SWITCH_PORT(13, 6, internal)
+ SWITCH_PORT(14, 7, internal)
+ SWITCH_PORT(15, 8, internal)
+ SWITCH_SFP_PORT(24, 9, rgmii-id)
+ SWITCH_SFP_PORT(26, 10, rgmii-id)
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl8382_d-link_dgs-1210.dtsi"
+
+/ {
+ compatible = "d-link,dgs-1210-16", "realtek,rtl838x-soc";
+ model = "D-Link DGS-1210-16";
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ EXTERNAL_SFP_PHY(24)
+ EXTERNAL_SFP_PHY(25)
+ EXTERNAL_SFP_PHY(26)
+ EXTERNAL_SFP_PHY(27)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(0, 1, qsgmii)
+ SWITCH_PORT(1, 2, qsgmii)
+ SWITCH_PORT(2, 3, qsgmii)
+ SWITCH_PORT(3, 4, qsgmii)
+ SWITCH_PORT(4, 5, qsgmii)
+ SWITCH_PORT(5, 6, qsgmii)
+ SWITCH_PORT(6, 7, qsgmii)
+ SWITCH_PORT(7, 8, qsgmii)
+
+ SWITCH_PORT(8, 9, internal)
+ SWITCH_PORT(9, 10, internal)
+ SWITCH_PORT(10, 11, internal)
+ SWITCH_PORT(11, 12, internal)
+ SWITCH_PORT(12, 13, internal)
+ SWITCH_PORT(13, 14, internal)
+ SWITCH_PORT(14, 15, internal)
+ SWITCH_PORT(15, 16, internal)
+
+ SWITCH_PORT(24, 17, qsgmii)
+ SWITCH_PORT(25, 18, qsgmii)
+ SWITCH_PORT(26, 19, qsgmii)
+ SWITCH_PORT(27, 20, qsgmii)
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl8382_d-link_dgs-1210.dtsi"
+
+/ {
+ compatible = "d-link,dgs-1210-28", "realtek,rtl838x-soc";
+ model = "D-Link DGS-1210-28";
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+
+ EXTERNAL_SFP_PHY(24)
+ EXTERNAL_SFP_PHY(25)
+ EXTERNAL_SFP_PHY(26)
+ EXTERNAL_SFP_PHY(27)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(0, 1, qsgmii)
+ SWITCH_PORT(1, 2, qsgmii)
+ SWITCH_PORT(2, 3, qsgmii)
+ SWITCH_PORT(3, 4, qsgmii)
+ SWITCH_PORT(4, 5, qsgmii)
+ SWITCH_PORT(5, 6, qsgmii)
+ SWITCH_PORT(6, 7, qsgmii)
+ SWITCH_PORT(7, 8, qsgmii)
+
+ SWITCH_PORT(8, 9, internal)
+ SWITCH_PORT(9, 10, internal)
+ SWITCH_PORT(10, 11, internal)
+ SWITCH_PORT(11, 12, internal)
+ SWITCH_PORT(12, 13, internal)
+ SWITCH_PORT(13, 14, internal)
+ SWITCH_PORT(14, 15, internal)
+ SWITCH_PORT(15, 16, internal)
+
+ SWITCH_PORT(16, 17, qsgmii)
+ SWITCH_PORT(17, 18, qsgmii)
+ SWITCH_PORT(18, 19, qsgmii)
+ SWITCH_PORT(19, 20, qsgmii)
+ SWITCH_PORT(20, 21, qsgmii)
+ SWITCH_PORT(21, 22, qsgmii)
+ SWITCH_PORT(22, 23, qsgmii)
+ SWITCH_PORT(23, 24, qsgmii)
+
+ SWITCH_PORT(24, 25, qsgmii)
+ SWITCH_PORT(25, 26, qsgmii)
+ SWITCH_PORT(26, 27, qsgmii)
+ SWITCH_PORT(27, 28, qsgmii)
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ led-boot = &led_power;
+ led-failsafe = &led_power;
+ led-running = &led_power;
+ led-upgrade = &led_power;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_power: power {
+ label = "green:power";
+ gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&gpio0 {
+ indirect-access-bus-id = <0>;
+};
+
+&spi0 {
+ status = "okay";
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x00000000 0x80000>;
+ read-only;
+ };
+ partition@80000 {
+ label = "u-boot-env";
+ reg = <0x00080000 0x40000>;
+ read-only;
+ };
+ partition@c0000 {
+ label = "u-boot-env2";
+ reg = <0x000c0000 0x40000>;
+ };
+ partition@280000 {
+ label = "firmware";
+ compatible = "denx,uimage";
+ reg = <0x00100000 0xd80000>;
+ };
+ partition@be80000 {
+ label = "kernel2";
+ reg = <0x00e80000 0x180000>;
+ };
+ partition@1000000 {
+ label = "sysinfo";
+ reg = <0x01000000 0x40000>;
+ };
+ partition@1040000 {
+ label = "rootfs2";
+ reg = <0x01040000 0xc00000>;
+ };
+ partition@1c40000 {
+ label = "jffs2";
+ reg = <0x01c40000 0x3c0000>;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "inaba,aml2-17gp", "realtek,rtl838x-soc";
+ model = "INABA Abaniact AML2-17GP";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <20>;
+
+ reset {
+ label = "reset";
+ gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+};
+
+&gpio0 {
+ indirect-access-bus-id = <0>;
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "u-boot-env";
+ reg = <0x80000 0x10000>;
+ read-only;
+ };
+
+ partition@90000 {
+ label = "u-boot-env2";
+ reg = <0x90000 0x10000>;
+ };
+
+ partition@a0000 {
+ label = "jffs2_cfg";
+ reg = <0xa0000 0x400000>;
+ read-only;
+ };
+
+ partition@4a0000 {
+ label = "jffs2_log";
+ reg = <0x4a0000 0x100000>;
+ read-only;
+ };
+
+ partition@5a0000 {
+ compatible = "openwrt,uimage", "denx,uimage";
+ label = "firmware";
+ reg = <0x5a0000 0xd30000>;
+ openwrt,ih-magic = <0x83800000>;
+ };
+
+ partition@12d0000 {
+ label = "runtime2";
+ reg = <0x12d0000 0xd30000>;
+ };
+ };
+ };
+};
+
+ðernet0 {
+ mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+
+ EXTERNAL_PHY(24)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(8, 1, internal)
+ SWITCH_PORT(9, 2, internal)
+ SWITCH_PORT(10, 3, internal)
+ SWITCH_PORT(11, 4, internal)
+ SWITCH_PORT(12, 5, internal)
+ SWITCH_PORT(13, 6, internal)
+ SWITCH_PORT(14, 7, internal)
+ SWITCH_PORT(15, 8, internal)
+
+ SWITCH_PORT(16, 9, qsgmii)
+ SWITCH_PORT(17, 10, qsgmii)
+ SWITCH_PORT(18, 11, qsgmii)
+ SWITCH_PORT(19, 12, qsgmii)
+ SWITCH_PORT(20, 13, qsgmii)
+ SWITCH_PORT(21, 14, qsgmii)
+ SWITCH_PORT(22, 15, qsgmii)
+ SWITCH_PORT(23, 16, qsgmii)
+
+ port@24 {
+ reg = <24>;
+ label = "wan";
+ phy-handle = <&phy24>;
+ phy-mode = "qsgmii";
+ };
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_zyxel_gs1900.dtsi"
+
+/ {
+ compatible = "zyxel,gs1900-24hp-v2", "realtek,rtl838x-soc";
+ model = "ZyXEL GS1900-24HP v2 Switch";
+
+ /* i2c of the left SFP cage: port 25 */
+ i2c0: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp0: sfp-p25 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* i2c of the right SFP cage: port 26 */
+ i2c1: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp1: sfp-p26 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&mdio {
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+
+ INTERNAL_PHY(24)
+ INTERNAL_PHY(26)
+};
+
+&switch0 {
+ ports {
+ SWITCH_PORT(0, 1, qsgmii)
+ SWITCH_PORT(1, 2, qsgmii)
+ SWITCH_PORT(2, 3, qsgmii)
+ SWITCH_PORT(3, 4, qsgmii)
+ SWITCH_PORT(4, 5, qsgmii)
+ SWITCH_PORT(5, 6, qsgmii)
+ SWITCH_PORT(6, 7, qsgmii)
+ SWITCH_PORT(7, 8, qsgmii)
+
+ SWITCH_PORT(8, 9, internal)
+ SWITCH_PORT(9, 10, internal)
+ SWITCH_PORT(10, 11, internal)
+ SWITCH_PORT(11, 12, internal)
+ SWITCH_PORT(12, 13, internal)
+ SWITCH_PORT(13, 14, internal)
+ SWITCH_PORT(14, 15, internal)
+ SWITCH_PORT(15, 16, internal)
+
+ SWITCH_PORT(16, 17, qsgmii)
+ SWITCH_PORT(17, 18, qsgmii)
+ SWITCH_PORT(18, 19, qsgmii)
+ SWITCH_PORT(19, 20, qsgmii)
+ SWITCH_PORT(20, 21, qsgmii)
+ SWITCH_PORT(21, 22, qsgmii)
+ SWITCH_PORT(22, 23, qsgmii)
+ SWITCH_PORT(23, 24, qsgmii)
+
+
+ port@24 {
+ reg = <24>;
+ label = "lan25";
+ phy-mode = "1000base-x";
+ managed = "in-band-status";
+ sfp = <&sfp0>;
+ };
+
+ port@26 {
+ reg = <26>;
+ label = "lan26";
+ phy-mode = "1000base-x";
+ managed = "in-band-status";
+ sfp = <&sfp1>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#define STRINGIZE(s) #s
+#define LAN_LABEL(p, s) STRINGIZE(p ## s)
+#define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
+
+#define INTERNAL_PHY(n) \
+ phy##n: ethernet-phy@##n { \
+ reg = <##n>; \
+ compatible = "ethernet-phy-ieee802.3-c22"; \
+ phy-is-integrated; \
+ };
+
+#define EXTERNAL_PHY(n) \
+ phy##n: ethernet-phy@##n { \
+ reg = <##n>; \
+ compatible = "ethernet-phy-ieee802.3-c22"; \
+ };
+
+#define EXTERNAL_SFP_PHY(n) \
+ phy##n: ethernet-phy@##n { \
+ compatible = "ethernet-phy-ieee802.3-c22"; \
+ sfp; \
+ media = "fibre"; \
+ reg = <##n>; \
+ };
+
+#define SWITCH_PORT(n, s, m) \
+ port@##n { \
+ reg = <##n>; \
+ label = SWITCH_PORT_LABEL(s) ; \
+ phy-handle = <&phy##n>; \
+ phy-mode = #m ; \
+ };
+
+#define SWITCH_SFP_PORT(n, s, m) \
+ port@##n { \
+ reg = <##n>; \
+ label = SWITCH_PORT_LABEL(s) ; \
+ phy-handle = <&phy##n>; \
+ phy-mode = #m ; \
+ fixed-link { \
+ speed = <1000>; \
+ full-duplex; \
+ }; \
+ };
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "realtek,rtl838x-soc";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ frequency = <500000000>;
+
+ cpu@0 {
+ compatible = "mips,mips4KEc";
+ reg = <0>;
+ };
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,38400";
+ };
+
+ cpuintc: cpuintc {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ intc: rtlintc {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "realtek,rt8380-intc";
+ reg = <0xb8003000 0x20>;
+ };
+
+ spi0: spi@b8001200 {
+ status = "okay";
+
+ compatible = "realtek,rtl838x-nor";
+ reg = <0xb8001200 0x100>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ uart0: uart@b8002000 {
+ status = "okay";
+
+ compatible = "ns16550a";
+ reg = <0xb8002000 0x100>;
+
+ clock-frequency = <200000000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <31>;
+
+ reg-io-width = <1>;
+ reg-shift = <2>;
+ fifo-size = <1>;
+ no-loopback-test;
+ };
+
+ uart1: uart@b8002100 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&enable_uart1>;
+
+ status = "okay";
+
+ compatible = "ns16550a";
+ reg = <0xb8002100 0x100>;
+
+ clock-frequency = <200000000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <30>;
+
+ reg-io-width = <1>;
+ reg-shift = <2>;
+ fifo-size = <1>;
+ no-loopback-test;
+ };
+
+ gpio0: gpio-controller@b8003500 {
+ compatible = "realtek,rtl838x-gpio";
+ reg = <0xb8003500 0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupts = <23>;
+ };
+
+ gpio1: rtl8231-gpio {
+ status = "disabled";
+ compatible = "realtek,rtl8231-gpio";
+ #gpio-cells = <2>;
+ indirect-access-bus-id = <0>;
+ gpio-controller;
+ };
+
+ pinmux: pinmux@bb001000 {
+ compatible = "pinctrl-single";
+ reg = <0xbb001000 0x4>;
+
+ pinctrl-single,bit-per-mux;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x1>;
+ #pinctrl-cells = <2>;
+
+ enable_uart1: pinmux_enable_uart1 {
+ pinctrl-single,bits = <0x0 0x10 0x10>;
+ };
+ };
+
+ ethernet0: ethernet@bb00a300 {
+ status = "okay";
+
+ compatible = "realtek,rtl838x-eth";
+ reg = <0xbb00a300 0x100>;
+ interrupt-parent = <&intc>;
+ interrupts = <24>;
+ #interrupt-cells = <1>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ switch0: switch@bb000000 {
+ status = "okay";
+
+ interrupt-parent = <&intc>;
+ interrupts = <20>;
+
+ compatible = "realtek,rtl83xx-switch";
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#define STRINGIZE(s) #s
+#define LAN_LABEL(p, s) STRINGIZE(p ## s)
+#define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
+
+#define INTERNAL_PHY(n) \
+ phy##n: ethernet-phy@##n { \
+ reg = <##n>; \
+ compatible = "ethernet-phy-ieee802.3-c22"; \
+ phy-is-integrated; \
+ };
+
+#define EXTERNAL_PHY(n) \
+ phy##n: ethernet-phy@##n { \
+ reg = <##n>; \
+ compatible = "ethernet-phy-ieee802.3-c22"; \
+ };
+
+#define EXTERNAL_SFP_PHY(n) \
+ phy##n: ethernet-phy@##n { \
+ compatible = "ethernet-phy-ieee802.3-c22"; \
+ sfp; \
+ media = "fibre"; \
+ reg = <##n>; \
+ };
+
+#define SWITCH_PORT(n, s, m) \
+ port@##n { \
+ reg = <##n>; \
+ label = SWITCH_PORT_LABEL(s) ; \
+ phy-handle = <&phy##n>; \
+ phy-mode = #m ; \
+ };
+
+#define SWITCH_SFP_PORT(n, s, m) \
+ port@##n { \
+ reg = <##n>; \
+ label = SWITCH_PORT_LABEL(s) ; \
+ phy-handle = <&phy##n>; \
+ phy-mode = #m ; \
+ fixed-link { \
+ speed = <1000>; \
+ full-duplex; \
+ }; \
+ };
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "realtek,rtl838x-soc";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ frequency = <800000000>;
+
+ cpu@0 {
+ compatible = "mips,mips34Kc";
+ reg = <0>;
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,38400";
+ };
+
+ cpuintc: cpuintc {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ intc: rtlintc {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "realtek,rt9300-intc";
+ reg = <0xb8003000 0x20>;
+ };
+
+ osc: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <1>;
+ clock-frequency = <175000000>;
+ clock-output-names = "osc";
+ };
+
+ timer: timer@b8003200 {
+ compatible = "realtek,rtl9300-timer";
+ reg = <0xb8003200 0x60>;
+ interrupt-parent = <&intc>;
+ interrupts = <8>;
+ interrupt-names = "ostimer";
+ clocks = <&osc 0>;
+ };
+
+ spi0: spi@b8001200 {
+ status = "okay";
+
+ compatible = "realtek,rtl838x-nor";
+ reg = <0xb8001200 0x100>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ uart0: uart@b8002000 {
+ compatible = "ns16550a";
+ reg = <0xb8002000 0x100>;
+
+ clock-frequency = <175000000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <30>;
+
+ reg-io-width = <1>;
+ reg-shift = <2>;
+ fifo-size = <1>;
+ no-loopback-test;
+
+ status = "okay";
+ };
+
+ uart1: uart@b8002100 {
+ compatible = "ns16550a";
+ reg = <0xb8002100 0x100>;
+
+ clock-frequency = <175000000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <31>;
+
+ reg-io-width = <1>;
+ reg-shift = <2>;
+ fifo-size = <1>;
+ no-loopback-test;
+
+ status = "okay";
+ };
+
+ gpio0: gpio-controller@b8003500 {
+ compatible = "realtek,rtl838x-gpio";
+ reg = <0xb8003500 0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupts = <31>;
+ };
+
+ ethernet0: ethernet@bb00a300 {
+ status = "okay";
+ compatible = "realtek,rtl838x-eth";
+ reg = <0xbb00a300 0x100>;
+ interrupt-parent = <&intc>;
+ interrupts = <24>;
+ #interrupt-cells = <1>;
+ phy-mode = "internal";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ switch0: switch@bb000000 {
+ status = "okay";
+
+ interrupt-parent = <&intc>;
+ interrupts = <20>;
+
+ compatible = "realtek,rtl83xx-switch";
+ };
+};
PROFILES = Default
KERNEL := kernel-bin | append-dtb | gzip | uImage gzip
KERNEL_INITRAMFS := kernel-bin | append-dtb | gzip | uImage gzip
- DEVICE_DTS_DIR := ../dts
+ DEVICE_DTS_DIR := ../dts-$(KERNEL_PATCHVER)
DEVICE_DTS = $$(SOC)_$(1)
IMAGES := sysupgrade.bin
IMAGE/sysupgrade.bin := append-kernel | pad-to 64k | append-rootfs | pad-rootfs | \
projects / thirdparty / openwrt.git / commitdiff
