]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
Octeontx2-af: RPM: Register driver with PCI subsys IDs
authorHariprasad Kelam <hkelam@marvell.com>
Mon, 24 Feb 2025 03:56:03 +0000 (09:26 +0530)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 29 May 2025 09:13:06 +0000 (11:13 +0200)
[ Upstream commit fc9167192f29485be5621e2e9c8208b717b65753 ]

Although the PCI device ID and Vendor ID for the RPM (MAC) block
have remained the same across Octeon CN10K and the next-generation
CN20K silicon, Hardware architecture has changed (NIX mapped RPMs
and RFOE Mapped RPMs).

Add PCI Subsystem IDs to the device table to ensure that this driver
can be probed from NIX mapped RPM devices only.

Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
Link: https://patch.msgid.link/20250224035603.1220913-1-hkelam@marvell.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
drivers/net/ethernet/marvell/octeontx2/af/rvu.h

index e43c4608d3ba33df68e73c4136ad1ae67ba3bcd1..971993586fb49da9b6039c52518acc2f3197b618 100644 (file)
@@ -66,8 +66,18 @@ static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool en);
 /* Supported devices */
 static const struct pci_device_id cgx_id_table[] = {
        { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_CGX) },
-       { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM) },
-       { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM) },
+       { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM,
+         PCI_ANY_ID, PCI_SUBSYS_DEVID_CN10K_A) },
+       { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM,
+         PCI_ANY_ID, PCI_SUBSYS_DEVID_CNF10K_A) },
+       { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM,
+         PCI_ANY_ID, PCI_SUBSYS_DEVID_CNF10K_B) },
+       { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM,
+         PCI_ANY_ID, PCI_SUBSYS_DEVID_CN10K_B) },
+       { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM,
+         PCI_ANY_ID, PCI_SUBSYS_DEVID_CN20KA) },
+       { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM,
+         PCI_ANY_ID, PCI_SUBSYS_DEVID_CNF20KA) },
        { 0, }  /* end of table */
 };
 
index a383b5ef5b2d8daba3122deb2f696c4e3d00ecf3..60f085b00a8cc0e03a611790fea6dbb7e336a77b 100644 (file)
@@ -30,6 +30,8 @@
 #define PCI_SUBSYS_DEVID_CNF10K_A             0xBA00
 #define PCI_SUBSYS_DEVID_CNF10K_B              0xBC00
 #define PCI_SUBSYS_DEVID_CN10K_B               0xBD00
+#define PCI_SUBSYS_DEVID_CN20KA                0xC220
+#define PCI_SUBSYS_DEVID_CNF20KA               0xC320
 
 /* PCI BAR nos */
 #define        PCI_AF_REG_BAR_NUM                      0